sii3114 Silicon image, sii3114 Datasheet - Page 62

• Manufacturer Part Number: sii3114
• Description: Pci To Serial Ata Controller
• Manufacturer: Silicon image

SiI3114 PCI to Serial ATA Controller
Data Sheet
PRD Table Address – Channel X
Address Offset: 04
Access Type: Read/Write
Reset Value: 0x0000_0000
This register defines the PRD Table Address register for Channel X in the SiI3114. The register bits are defined
below.
PCI Bus Master2 – Channel X
Address Offset: 10
Access Type: Read/Write
Reset Value: 0x0808_XX00 (Chnl 0/2) / 0x0008_0000 (Chnl 1/3)
This register defines the second PCI bus master register for Channel X in the SiI3114. The system must access
these register bits through this address to enable the Large Block Transfer Mode.
The register bits are defined below.
SiI-DS-0103-D
• Bit [03] : PBM Rd-Wr (R/W) – PCI Bus Master Read-Write Control. This bit is set to specify a DMA write
• Bit [02] : Reserved (R). This bit is reserved and returns zero on a read.
• Bit [01] : Interrupt Steering (R/W). This bit is set to 1 to allow interrupts from all four channels. If the bit is a
• Bit [00] : PBM Enable (R/W) – PCI Bus Master Enable – Channel X . This bit is set to enable PCI bus
• Bit [31:02] : PRD Table Address (R/W) – Physical Region Descriptor Table Address. This bit field defines
• Bit [01:00] : Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [31:24] : (R) These bits are copies of PCI Bus Master Channel X+1 bits. This bit field (and bits 15 to 5)
• Bit [23] : PBM Simplex (R) – PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to
operation from Channel X to system memory. This bit is cleared to specify a DMA read operation from
system memory to the Channel X device.
0 (the default), only interrupts from the channel selected by the “shadow” Device Select bit are enabled.
This bit appears only in the Channel 2 (offset 200
00
master operations for Channel X . PCI bus master operations can be halted by clearing this bit, but will
erase all state information in the control logic. If this bit is cleared while the PCI bus master is active, the
operation will be aborted and the data discarded. While this bit is set, accessing Channel X Task File or
PIO data registers will be terminated with Target-Abort.
the Descriptor Table base address.
appears only in the Channel 0 (offset 10
the Channel 1 (offset 18
indicate that all channels can operate as PCI bus master at any time.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
H
), Channel 1 (offset 08
Reserved for Chnl 1/3
H
H
/ 0C
/ 18
H
H
/ 210
/ 204
H
H
H
) and Channel 3 (offset 218
H
/ 218
/ 20C
), and Channel 3 (offset 208
H
H
H
PRD Table Address
) and Channel 2 (offset 210
H
54
) register; this bit is reserved in the Channel 0 (offset
H
) registers.
H
) registers.
Reserved for Chnl 1/3
Software
H
) registers; this bit field is reserved in
© 2007 Silicon Image, Inc.
Silicon Image, Inc.