PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 18

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

3.2.8
3.2.9
TEST SIGNALS
POWER AND GROUND SIGNALS
Name
T_DI1
T_DI2
T_MODECTL
T_RI
XCLK_OUT
T_RI
TEST_CE0
Name
P_VDDA
P_VSSA
S_VDDA
S_VSSA
VDD
Pin #
Y21
AA4
C1
W22
D3
W22
Y23
Pin #
A21
D16
AB21
Y16
D9, D11, D13, D15,
J4, J20, L4, L20, N4,
N20, R4, R20, Y9,
Y11, Y13, Y15
Page 18 of 77
Type
Type
IU
IU
ID
P
P
P
P
P
I
I
I
I
Description
PLL Bypass Control for PCI-X Mode. The strapped
value of this pin (at P_RST# deassertion) controls
whether the internal PLL’s are bypassed in PCI-X mode.
HIGH: PLL’s are used in PCI-X mode
LOW: PLL’s are bypassed in PCI-X mode
Shorten Initialization Period. Controls the period for
the following signals during initialization.
LOW: Shorten periods
HIGH: Normal initialization
PLL Test Control. Controls along with the internal
PLL testing.
* P_PLL enabled, S_PLL disabled
**P_PLL disabled, S_PLL enabled
PLL Bypass Control for PCI Mode. The strapped
value of this pin (at T_RI) controls whether the internal
PLL’s are bypassed in PCI mode.
1: PLL’s are bypassed in PCI mode
0 and T_MODECTL=0: PLL’s are used in PCI mode
Reserved. Chip testing only. Tie LOW for normal
operation.
Description
2.5V Power: Power supply to the PLL for the primary
clock domain.
2.5V Power: Ground for the PLL for the primary clock
domain.
2.5V Power: Power supply to the PLL for the secondary
clock domain.
2.5V Power: Ground for the PLL for the secondary
clock domain.
2.5 Power: Power supply for the internal logic
T_RI
T
T
T
T
T
T
T
T
PIRSTDLY
XCAP
SIRSTDLY
SRSTDLY
PIRSTDLY
XCAP
SIRSTDLY
SRSTDLY
H
H
L
– See Table 7-2
– 6 Primary Clocks
– See Table 7-2
– See Table 7-2
– See Table 7-2
T_MODECTL
– 11 Secondary Clocks + 7 Primary Clocks
- 5 Primary Clocks
- 40 Secondary Clocks
ADVANCE INFORMATION
H
H
L
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
XCLK_OUT
S_CLK**
P_CLK*
Z
PI7C21P100