PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 59

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

8.1.53
8.1.54
8.1.55
NEXT CAPABILITY POINTER REGISTER – OFFSET 80h
PCI-X SECONDARY STATUS REGISTER – OFFSET 80h
PCI-X BRIDGE PRIMARY STATUS REGISTER – OFFSET 84h
BIT
15:8
BIT
31:25
24:22
21
20
19
18
17
16
BIT
31:22
FUNCTION
Next Capability Pointer
FUNCTION
RESERVED
Secondary Clock
Frequency
Split Request Delayed
Split Completion
Overrun
Unexpected Split
Completion
Split Completion
Discarded
133MHz Capable
64-bit Device
FUNCTION
RESERVED
TYPE
RO
TYPE
RO
RW
TYPE
RO
RO
RW
RW
RW
RO
RO
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DESCRIPTION
Next Capability Pointer
Returns 90h when read to indicate that there are more list items in the
Capabilities List.
DESCRIPTION
Reserved. Returns 0000000 when read.
Secondary Clock Frequency
Enables the configuration software to determine what mode and what
frequency PI7C21P100 set the secondary bus to the last time the
secondary RST# was asserted.
VALUE
000
001
010
011
1xx
Split Request Delayed
0: The bridge has not delayed a split request
1: The bridge has delayed a split request because the bridge cannot
forward a transaction to the secondary bus because there isn’t enough
room within the limit specified in the split transaction commitment
limit field in the downstream split transaction control register.
Reset to 0
Split Completion Overrun
0: PI7C21P100 has accepted all split completions.
1: PI7C21P100 has terminated a split completion on the secondary
bus with retry or disconnect at the next ADB because the bridge
buffers were full.
Reset to 0
Unexpected Split Completion
0: No unexpected split completion has been received.
1: An unexpected split completion has been received with the
requested ID equal to the bridge’s secondary bus number, device
number 00h, and function number 0 on the bridge secondary
interface.
Reset to 0
Split Completion Discarded
0: No split completion has been discarded.
1: A split completion moving toward the secondary bus has been
discarded by the bridge because the requester would not accept it.
Reset to 0.
133MHz Capable
Returns 1 when read to indicate PI7C21P100 is capable of 133MHz
operation on the secondary interface.
64-bit Device
Returns a 1 when the AD interface is 64-bits wide on the secondary
bus and 64BIT_DEV#=1. Returns a 0 when 64BIT_DEV#=0.
DESCRIPTION
Reserved. Returns 00000000 when read.
MAX CLOCK FREQUENCY
conventional mode
66 MHz
100 MHz
133 MHz
Reserved
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
MIN CLK PERIOD
N/A
15ns
10ns
7.5ns
Reserved
PI7C21P100