PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 38

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

7.3
7.4
Table 7-1 DELAY TIMES FOR DE-ASSERTION OF S_RST#
Table 7-2 DE-ASSERTION OF S_RST#
BUS PARKING & BUS WIDTH DETERMINATION
Bus parking refers to driving the AD[31:0], CBE[3:0], and PAR lines to a known value while
the bus is idle. In general, the device implementing the bus arbiter is responsible for parking
the bus or assigning another device to park the bus. A device parks the bus when the bus is
idle, its bus grant is asserted, and the device’s request is not asserted. The AD[31:0],
CBE[3:0], and PAR signals are driven LOW after assertion of S_RST#.
PI7C21P100 will assert S_REQ64# for at least 10 PCI clock cycles to allow devices to
determine whether they are connected on a 64-bit bus or 32-bit bus.
SECONDARY DEVICE MASKING
Secondary devices can be masked through configuration or power strapping of the secondary
bus private device mask register. The process of converting Type 1 configuration transactions
to Type 0 configuration transactions is modified by the contents of the secondary bus private
device mask register. A configuration transaction that targets a device masked by this register
is routed to device 15. Secondary bus architectures which are designed to support masking of
T
T
T
T
Note: Primary and secondary clock cycles refer to clock cycles whose period is determined by the P_CLK and
S_CLK inputs.
PIRSTDLY
XCAP
SRSTDLY
SIRSTDLY
Conventional PCI
7 primary clock
cycles
6675 primary clock
cycles
11 secondary and 7
primary clock
cycles
16 secondary clock
cycles
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PCI-X 66
6678 primary clock
cycles
100us – 133us
6675 primary clock
cycles
100us – 133us
11 secondary and 7
primary clock
cycles
6687 secondary
clock cycles
100us – 133us
PCI-X 100
13350 primary
clock cycles
133us – 200us
13347 primary
clock cycles
133us – 200us
11 secondary and 7
primary clock
cycles
13350 secondary
clock cycles
133us – 200us
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
PCI-X 133
13350 primary
clock cycles
100us – 133us
13347 primary
clock cycles
100us – 133us
11 secondary and 7
primary clock
cycles
13350 secondary
clock cycles
100us – 133us
PI7C21P100