PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 54

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

8.1.40
8.1.41
ARBITER ENABLE REGISTER – OFFSET 54h
ARBITER PRIORITY REGISTER – OFFSET 58h
BIT
0
BIT
7
6
5
4
3
2
1
0
BIT
7
6
5
4
3
FUNCTION
External Arbiter
FUNCTION
RESERVED
Enable Arbiter 6
Enable Arbiter 5
Enable Arbiter 4
Enable Arbiter 3
Enable Arbiter 2
Enable Arbiter 1
Enable Arbiter 0
FUNCTION
RESERVED
Arbiter Priority 6
Arbiter Priority 5
Arbiter Priority 4
Arbiter Priority 3
TYPE
RO
TYPE
RW
RW
RW
RW
RW
RW
RW
TYPE
RW
RW
RW
RW
RO
RO
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DESCRIPTION
External Arbiter
0: Enable internal arbiter.
1: Disable internal arbiter.
Reset to 0 or 1 according to the value of S_ARB# during the reset. If
S_ARB# is tied LOW, then returns 0 when read. If S_ARB# is tied
HIGH, then returns 1 when read.
DESCRIPTION
Reserved. Returns 0 when read.
Enable Arbiter 6
0: Disable arbitration for master 6
1: Enable arbitration for master 6
Reset to 1
Enable Arbiter 5
0: Disable arbitration for master 5
1: Enable arbitration for master 5
Reset to 1
Enable Arbiter 4
0: Disable arbitration for master 4
1: Enable arbitration for master 4
Reset to 1
Enable Arbiter 3
0: Disable arbitration for master 3
1: Enable arbitration for master 3
Reset to 1
Enable Arbiter 2
0: Disable arbitration for master 2
1: Enable arbitration for master 2
Reset to 1
Enable Arbiter 1
0: Disable arbitration for master 1
1: Enable arbitration for master 1
Reset to 1
Enable Arbiter 0
0: Disable arbitration for internal bridge request
1: Enable arbitration for internal bridge request
Reset to 1
DESCRIPTION
Reserved. Returns 0 when read.
Arbiter Priority 6
0: Low priority request to master 6
1: High priority request to master 6
Reset to 0
Arbiter Priority 5
0: Low priority request to master 5
1: High priority request to master 5
Reset to 0
Arbiter Priority 4
0: Low priority request to master 4
1: High priority request to master 4
Reset to 0
Arbiter Priority 3
0: Low priority request to master 3
1: High priority request to master 3
Reset to 0
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
PI7C21P100