AD362 AD [Analog Devices], AD362 Datasheet - Page 5

• Manufacturer Part Number: AD362
• Description: PrecisionSample-and-Hold with 16-Channel Multiplexer
• Manufacturer: AD [Analog Devices]

.
I
.
The normal sequence of events is as follows:
4. The ADC goes into its conversion routine. Since the sample-
NOTE:
Valid OutPut Data
that the conversion is complete. Successive approximation
delay built in or the final data bit will lag Status by approx-
imately SOns. This will result in two problems:
1. The appropriate Channel Select Address is latched into the
2. A Convert Start command is issued to the ADC which, in
3. The ADC Status controls the sample-and-hold. When the
5. The ADC indicates completion of its conversion by return-
6. If the input signal has changed full-scale (different channels
Mter allowing a suitable interval for the sample-and-hold to
stabilize at its new value, another Convert Start command may
be issued to the ADC.
Not all ADCs have all data bits available when Status indicates
ADCs based on the 250213/4 type of register must have a Status
1. The sample-and-hold will return to Sample, disturbing the
2. If the falling edge of Status is being used to load the data
An external lOOns delay or use of an ADC with a valid Status
output is necessary to prevent this problem. The applications
shown in this data sheet ensure that all data bits will be valid.
The following test may be made to determine if the ADC
Status timing is correct:
1. Connect the ADC under test as shown in Figure 4.
address register. Time is allowed for the multiplexers to
settle.
response, indicates that it is "busy" by placing a Logic "1"
on its Status line.
ADC is"busy", the sample-and-hold is in the Hold mode.
and-hold is holding the proper analog value, the address
may be updated during conversion. Thus multiplexer set-
analog input to the ADC as it is attempting to convert the
least significant bit. This may result in an error.
into a register, the least significant bit will not be valid
when loaded.
tling time can coincide with conversion and need not affect
throughput rate.
ing Status to Logic "0". The sample-and-hold returns to
the Sample mode.
may have widely-varying data) the sample-and-hold will
typically require 10 microseconds to "acquire" the next
input to sufficient accuracy for 12-bit conversion.
20""
-15V
+15V
51<"
51<"
CHANNEL A "1"~
CHANNEL
Figure4. ADC Status Valid Test
"STATUS"
"LSB"
B
"o"_'_~
ANALOG
INPUT
UNDER
--.
'I
ADC
I
I
I
g~G,'lAL
OUTPUTS
I
,
: VALID DATA
I
.--STATUSDELAY
TEST
STATUS
jf
:
I LSB
MSB
BIT 2
--
-5-
4. Vary the analog input control to confirm that the LSB
The AD362 features an internal analog switch that configures
the Analog Input Section in either a 16-channel single-ended
or 8-channel differential mode. This switch is controlled by a
TTL logic input applied to pin 1 of the Analog Input Section:
When in the differential mode, a differential source may be
Sin~le-Ended/Differential
applied between corresponding "High" and "Low" analog
input channels.
control to command the appropriate mode. In this case, four
2. Trigger the oscilloscope on Status. Delay the display such
3. Observe the LSB data output of the ADC.
It is possible to mix SE and DIFF inputs by using the mode
effect of this delay may be eliminated by changing modes
while a conversion is in progress (with the sample-and-hold
in the "Hold" mode). When SE and DIFF signals are being
measuring 16 sources individually andlor measuring differences
between pairs of those sources.
Table 1 is the truth table for input channel addressing in both
microseconds must be allowed for the output of the Analog
Input Section to settle to within :to.OI % of its final value, but
if the mode is switched concurrent with changing the channel
address, no significant additional delay is introduced. The
processed concurrently, the DIFF signals must be applied
between corresponding "High" and "Low" analog input chan-
nels. Another application of this feature is the capability of
Input Channel Addressin~
the single-ended and differential modes. The 16 single-ended
channels may be addressed by applying the corresponding
AE, AD, AI, A2 (pins 28-31).
eight channels are addressed by applying the appropriate
digital code to AD, Al and A2; AE must be enabled with a
Logic "1 ". Internal logic monitors the status of the SE/DIFF
Mode input and addresses the multiplexers singularly or in
digital number to the four Input Chanl1el Select address bits,
pairs as required.
that Status is mid-screen.
transition precedes the Status transition.
"0": Single-Ended (16 channels)
"1 ": Differential (8 channels)
AE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
--...-
Table 1. Input Channel Addressing Truth Table
A2
ADDRESS
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
AO
0
0
0
!
0
0
0
0
0
1
1
1
1
1
1
1
~
Mode Control
ON CHANNEL (Pin Number)
~-Q~l
12 (23)
14 (19)
0
1 (10)
2
3
4
5
6
7
8
9
10 (25)
11 (24)
13 (22)
In the differential mode, the
Ended
----------
(11)
(27)
(26)
(8)
(6)
(4)
m
(7)
(5)
Differential
"Hi"
4 (7)
5 (6)
6 (5)
7 ~4)_-
3 (8)
0 (11)
2 (9)
1 (10)
None
None
None
None
~~
None
None
None
---
6 (19)
7 (18)
5 (23)
5 (22)
2 (25)
3 (24)
0 (27)
1 (26)
"La"