AD362 AD [Analog Devices], AD362 Datasheet - Page 7

• Manufacturer Part Number: AD362
• Description: PrecisionSample-and-Hold with 16-Channel Multiplexer
• Manufacturer: AD [Analog Devices]

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The AD362 has been designed to interface directly to most
4. If StatUs is being used to latch output data, it must not
Complete system throughput performance is determined by
combining the worst-case specifications of the AD362 and the
ADC. If guaranteed system performance is required, the
AD363 and AD364 are recommended. The AD363 includes
an AD362 and an AD572 12-bit, 25-microsecond precision
ADC. The AD364 consists of an AD362 and an AD574 12-bit,
microprocessor-compatible,
as a complete, two-package system; data sheets are available
upon request.
analog to digital converters; often no additional components
are required and only two interconnections
The direct interface requirements for the ADC are as follows:
2. Transition from "0" to "1" must occur at least 200ns
3. StatUs must not retUrn to "0" before the LSB decision is
Interfacing to Popular Analog to Digital Converters
1. The ADC StatUs output must be positive-true Logic ("1"
~,:~:2~~-~!:.~
during conversion).
before the most significant bit decision is made (successive
approximation ADC) or before input integration starts
(integrating type ADC).
made (see page 5).
retUrn to Logic "0" until all output data bits are valid and
available.
ANALOG
INPUTS
1161
a. l2-Bit DAS Using AD362 and AD ADC80
AOJ62
CHANNEl
IANALOG ANALOG ADAOC80
SELECT
LATCH
SAMPLE/HOLD
OUT
DC POWER
Figure 7. Data Acquisition Systems Based on the AD362 and Popular ADC's
low cost ADC. Each is specified
CAPACITOR
:~~,~
HOLD
IN
-
I
I
CONVERT
START
.n.
must be made.
0
I STATUSOUTPUT
DATA STROBE
ITO OUTPUT
REGISTERI
DATA
BITS
OUT
(12)
-7-
The gating provided by Ul allows the applied convert com--
mand (CC) to initiate input hold at the AD362. CC must last
for more than 1.5JJs so that DR may then assume control
channel operation), the next convert command can be used to
single conversion operation, a IJJs delay of the falling edge of
of Hold. If conversion is continuous (consistent with multi-
DR may be used to signify valid data.
AD ADC80 is a 12-bit, 25-microsecond, low-cost ADC that
meets all of the requirements listed above. Throughput rate
is typically 30kHz with no missing codes over the operating
temperatUre range.
the AD571, a complete low cost 10-bit, 25-microsecond ADC.
4. DR precedes the enabling of the AD571 output 3-state
load the previously-converted data into an output register. For
Figure 7a shows the AD362 driving an AD ADC80. The
In this case, two of the above requirements are not met:
1. DR (DATA READY), as StatUs, is positive-true but. . .
2. DR does not indicate that a conversion is in progress until
3. DR does indicate conversion complete after the LSB deci-
Figure 7b shows a lO-bit application based on the AD362 and
sion is made, but. . .
gates by 500ns.
1.5JJs after conversion starts.
ANALOG
INPUTS
(IS)
~1.5~.
--::J
COMMAND
CONVERT
b. la-Bit DAS UsingAD362 and AD571
C
MIN
CHANNEL
SELECT
LATCH
1/474LSJ2
DC POWER
"'~f'::
~
DATA STROBE
(TO OUTPUT
REGISTER)
""
AO571
Me'
DR
DATA
BITS
OUT
(101
4