AD362 AD [Analog Devices], AD362 Datasheet - Page 6

• Manufacturer Part Number: AD362
• Description: PrecisionSample-and-Hold with 16-Channel Multiplexer
• Manufacturer: AD [Analog Devices]

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elements in the signal path). The effect of this delay may be
eliminated by performing the address change while a conver-
sion is in progress (with the sample-and-hold in the "Hold"
mode).
The AD362 is equipped with a latch for the Input Channel
mode. Eighteen microseconds must be allowed for the sample-
mand is issued.
have higher dielectric absorption (memory) and will cause
errors. CAUTION: Polystyrene capacitors will be destroyed
When the channel address is changed, six microseconds must
be allowed for the Analog Input Section to settle to within
:to.Ol % of its final output (including settling times of all
Inout Channel Address Latch
through to the multiplexers. A Logic "0" "freezes" the input
channeraddress present at the inputs at the "1"-to-"O" tran-
sition (level-triggered).
This feature is useful when input channel address information
The Sample-and-Hold Mode Control input (pin 13) is normally
digital converter. When a conversion is initiated by applying a
Convert Start command to the ADC, Status goes to Logic" 1",
and-hold to acquire ("catch up" to) the analog input to within
:to.Ol % of the final value before a new Convert Start com-
lectric must be used; i.e., Polystyrene (AD326KD only) or
Teflon (AD362KD or SD). Other types of capacitors may
if subjected to temperatures above +850 C. No capacitor is
required if the sample-and-hold is not used.
Select address bits. If the Latch Control pin (pin 32) is at
Logic "1 ", input channel select address information is passed
is provided from an address, data or control bus that may be
required to serv:ce many devices. The ability to latch an
address is helpful whenever the user has no control of when
address information may change.
Samole-and-Hold Mode Control
connected to the Status output (pin 20) from an analog to
putting the sample-and-hold into the "Hold" mode. This
"freezes" the information to be digitized for the period of
conversion. When the conversion is complete, Status returns
to Logic "0" and the sample-and-hold returns to the "Sample"
The purpose of a sample-and-hold is to "stop" fast changing
input signals long enough to be converted. In this application,
it also allows the user to change channels and/or SEt DIFF
mode while a conversion is in progress thus eliminating the
effects of multiplexer, analog switch and differential amplifier
settling times. If maximum throughput rate is required for
slowly changing signals, the Sample-and-Hold Mode Control
as close to pin 17 as possible. The capacitor provided with the
AD362KD is Polystyrene while the wider operating temperature
range of the AD362SD requires a Teflon capacitor (supplied).
Smaller capacitors will allow slightly faster operation, but only
with increased noise and decreased precision. 1000pF will
typically allow acquisition to 0.1 % in four microseconds.
Larger capacitors may be substituted to reduce noise, and
sample-to-hold offset, but acquisition time of the sample-and-
hold will be extended. If less than 12 bits of accuracy is re-
quired, a smaller capacitor may be used. This will shorten the
S/H acquisition time. In all cases, the proper capacitor die-
may be wired to ground (Logic "0") rather than to ADC
,tatus thus leaving the sample-and-hold in a continuous
;ample mode.
)f this capacitor is wired to pin 12, the other to analog ground
\ 2000pF capacitor is provided with each AD362. One side
lold Caoacitor
-6-
offset of the Analog Input Section. An example of such a case
Analo!! Inout Section Offset Adjust Circuit
Although the offset voltage of the AD362 may be adjusted,
special applications, however, it may be helpful to adjust the
would be if the input signals were small «10mV)
AD362 voltage offset and gain was to be inserted between the
AD362 and the ADC. To adjust the offset of the AD362, the
circuit shown in Figure 5 is recommended.
Grounding: Analog and digital signal grounds should be kept
externally for the system to operate properly. Preferably, this
connection is made at only one point, as close to the AD362
as possible. The case is connected internally to Digital Ground
tied common on the same card with the AD362, the digital
and analog grounds should be connected locally with back-to-
back general-purpose diodes as shown in Figure 6. This will
protect the AD362 from possible damage caused by voltages
occur if the key grounding card should be removed from the
overall system. The device will operate properly with as much
as :t200m V between grounds, however this difference will be
that adjustment is normally performed at the ADC. In some
ADC Section.
Other Considerations
in the analog ground circuit and inducing spurious analog sig-
nal noise. Analog Ground (pin 17) and Digital Ground (pin 2)
are not connected internally; these pins must be connected
to provide good electrostatic shielding. If the grounds are not
in excess of :tl volt between the ground systems which could
reflected directly as an input offset voltage.
Under normal conditions, all calibration is performed at the
separate where possible to prevent digital signals from flowing
Power Supply Bypassing: The :t15V and +5V power leads
should be capacitively bypassed to Analog Ground and Digital
Ground respectivelyfor optimum device performance.
tantalum types are recommended; these capacitors should be
located close to the system. It is not necessary to shunt these
capacitors with disc capacitors to provide additional high
frequency power supply decoupling since each power lead is
bypassed internally with a 0.039J.LFceramic capacitor.
Figure 5.
Figure 6. Ground-Fault Protection Diodes
CONNECTOR
CARD
OUTPUT
TO
AD362
16
DGND
AD362
Offset Voltage Adjustment
ANALOG
SECTION
AD362
INPUT
ADC
AGND
relative to
IJ.LF
,
88
8
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