ADSP-TS202S_06 AD [Analog Devices], ADSP-TS202S_06 Datasheet - Page 25

• Manufacturer Part Number: ADSP-TS202S_06
• Description: TigerSHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

Table 23. Reference Clocks—System Clock (SCLK) Cycle Time
1
2
3
4
5
6
Table 24. Reference Clocks—JTAG Test Clock (TCK) Cycle Time
Parameter
t
t
t
t
t
t
For more information, see
For more information, see Clock Domains on Page 9.
The value of (t
System clock transition times apply to minimum SCLK cycle time (t
Actual input jitter should be combined with ac specifications for accurate timing analysis.
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
Parameter
t
t
t
SCLK
SCLKH
SCLKL
SCLKF
SCLKR
SCLKJ
TCK
TCKH
TCKL
1, 2, 3
5, 6
SCLK
SCLK
TCK
/ SCLKRAT2-0) must not violate the specification for t
Description
System Clock Cycle Time
System Clock Cycle High Time
System Clock Cycle Low Time
System Clock Transition Time—Falling Edge
System Clock Transition Time—Rising Edge
System Clock Jitter Tolerance
Description
Test Clock (JTAG) Cycle Time
Test Clock (JTAG) Cycle High Time
Test Clock (JTAG) Cycle Low Time
Table 3 on Page
12.
Figure 11. Reference Clocks—JTAG Test Clock (TCK) Cycle Time
Figure 10. Reference Clocks—System Clock (SCLK) Cycle Time
t
t
TCKH
SCLKH
Rev. C | Page 25 of 48 | December 2006
t
t
SCLK
TCK
SCLK
t
t
TCKL
) only.
SCLKL
CCLK
4
.
SCLKRAT = 4×, 6×, 8×, 10×, 12×
Min
8
0.40 × t
0.40 × t
SCLK
SCLK
Max
50
0.60 × t
0.60 × t
1.5
1.5
500
Min
Greater of 30 or t
12
12
t
SCLKJ
SCLK
SCLK
Min
8
0.45 × t
0.45 × t
t
SCLKF
CCLK
× 4
SCLKRAT = 5×, 7×
SCLK
SCLK
t
SCLKR
Max
Max
50
0.55 × t
0.55 × t
1.5
1.5
500
ADSP-TS202S
SCLK
SCLK
Unit
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ps