ADSP-TS202S_06 AD [Analog Devices], ADSP-TS202S_06 Datasheet - Page 7

• Manufacturer Part Number: ADSP-TS202S_06
• Description: TigerSHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-TS202S processor accesses of the host as slave or pipe-
lined for host accesses of the ADSP-TS202S processor as slave.
Each protocol has programmable transmission parameters,
such as idle cycles, pipe depth, and internal wait cycles.
The host interface supports burst transactions initiated by a host
processor. After the host issues the starting address of the burst
and asserts the BRST signal, the DSP increments the address
internally while the host continues to assert BRST.
The host interface provides a deadlock recovery mechanism that
enables a host to recover from deadlock situations involving the
DSP. The BOFF signal provides the deadlock recovery mecha-
nism. When the host asserts BOFF, the DSP backs off the
current transaction and asserts HBG and relinquishes the
external bus.
The host can directly read or write the internal memory of the
ADSP-TS202S processor, and it can access most of the DSP reg-
isters, including DMA control (TCB) registers. Vector
interrupts support efficient execution of host commands.
Multiprocessor Interface
The ADSP-TS202S processor offers powerful features tailored
to multiprocessing DSP systems through the external port and
link ports. This multiprocessing capability provides highest
bandwidth for interprocessor communication, including
The external port and link ports provide integrated, glueless
multiprocessing support.
The external port supports a unified address space (see
that enables direct interprocessor accesses of each
ADSP-TS202S processor’s internal memory and registers. The
DSP’s on-chip distributed bus arbitration logic provides simple,
glueless connection for systems containing up to eight
ADSP-TS202S processors and a host processor. Bus arbitration
has a rotating priority. Bus lock supports indivisible read-
modify-write sequences for semaphores. A bus fairness feature
prevents one DSP from holding the external bus too long.
The DSP’s four link ports provide a second path for interproces-
sor communications with throughput of 4G bytes per second.
The cluster bus provides 1G bytes per second throughput—with
a total of 4G bytes per second interprocessor bandwidth (lim-
ited by SOC bandwidth).
SDRAM Controller
The SDRAM controller controls the ADSP-TS202S processor’s
transfers of data to and from external synchronous DRAM
(SDRAM) at a throughput of 32 bits or 64 bits per SCLK cycle
using the external port and SDRAM control pins.
The SDRAM interface provides a glueless interface with stan-
dard SDRAMs—16M bits, 64M bits, 128M bits, 256M bits, and
512M bits. The DSP supports directly a maximum of four banks
of 64M words × 32 bits of SDRAM. The SDRAM interface is
mapped in external memory in each DSP’s unified
memory map.
• Up to eight DSPs on a common bus
• On-chip arbitration for glueless multiprocessing
• Link ports for point-to-point communication
Rev. C | Page 7 of 48 | December 2006
Figure
3)
EPROM Interface
The ADSP-TS202S processor can be configured to boot from an
external 8-bit EPROM at reset through the external port. An
automatic process (which follows reset) loads a program from
the EPROM into internal memory. This process uses 16 wait
cycles for each read access. During booting, the BMS pin func-
tions as the EPROM chip select signal. The EPROM boot
procedure uses DMA Channel 0, which packs the bytes into
32-bit instructions. Applications can also access the EPROM
(write flash memories) during normal operation through DMA.
The EPROM or flash memory interface is not mapped in the
DSP’s unified memory map. It is a byte address space limited to
a maximum of 16M bytes (24 address bits). The EPROM or
flash memory interface can be used after boot via a DMA.
DMA CONTROLLER
The ADSP-TS202S processor’s on-chip DMA controller, with
14 DMA channels, provides zero-overhead data transfers with-
out processor intervention. The DMA controller operates
independently and invisibly to the DSP’s core, enabling DMA
operations to occur while the DSP’s core continues to execute
program instructions.
The DMA controller performs DMA transfers between internal
memory and external memory and memory-mapped peripher-
als, the internal memory of other DSPs on a common bus, a host
processor, or link port I/O; between external memory and exter-
nal peripherals or link port I/O; and between an external bus
master and internal memory or link port I/O. The DMA con-
troller performs the following DMA operations:
The DMA controller provides these additional features:
• External port block transfers. Four dedicated bidirectional
• Link port transfers. Eight dedicated DMA channels (four
• AutoDMA transfers. Two dedicated unidirectional DMA
• Flyby transfers. Flyby operations only occur through the
DMA channels transfer blocks of data between the DSP’s
internal memory and any external memory or memory-
mapped peripheral on the external bus. These transfers
support master mode and handshake mode protocols.
transmit and four receive) transfer quad-word data only
between link ports and between a link port and internal or
external memory. These transfers only use handshake
mode protocol. DMA priority rotates between the four
receive channels.
channels transfer data received from an external bus master
to internal memory or link port I/O. These transfers only
use slave mode protocol, and an external bus master must
initiate the transfer.
external port (DMA channel 0) and do not involve the
DSP’s core. The DMA controller acts as a conduit to trans-
fer data from an external I/O device and external SDRAM
memory. During a transaction, the DSP relinquishes the
ADSP-TS202S