XCS05-3BG100C XILINX [Xilinx, Inc], XCS05-3BG100C Datasheet
XCS05-3BG100C
Related parts for XCS05-3BG100C
XCS05-3BG100C Summary of contents
Page 1
... Unlimited reprogrammability • Low cost Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays Logic System Device Cells XCS05 and XCS05XL 238 XCS10 and XCS10XL 466 XCS20 and XCS20XL 950 XCS30 and XCS30XL 1368 XCS40 and XCS40XL 1862 Notes: 1 ...
Page 2
Spartan and Spartan-XL Families Field Programmable Gate Arrays General Overview Spartan series FPGAs are implemented with a regular, flex- ible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources (routing channels), and sur- ...
Page 3
R Spartan series devices achieve high-performance, low-cost operation through the use of an advanced architecture and semiconductor technology. Spartan devices provide system clock rates exceeding 80 MHz and internal performance in excess of 150 MHz. In contrast to other FPGA ...
Page 4
Spartan and Spartan-XL Families Field Programmable Gate Arrays G-LUT G4 G4 Logic G3 G3 Function G1- DIN F4 F4 Logic F3 F3 Function F1- F-LUT K ...
Page 5
R . Table 2: CLB Storage Element Functionality Mode CK EC Power- GSR Flip-Flop X X Operation Latch 1 1* Operation 0 1* (Spartan-XL) Both X 0 Legend: X Don’t care Rising edge (clock ...
Page 6
Spartan and Spartan-XL Families Field Programmable Gate Arrays Multiplexer Controlled by Configuration Program Figure 4: CLB Control Signal Interface The four internal control signals are: • EC: Enable Clock • SR: Asynchronous Set/Reset or H function ...
Page 7
R The register choice is made by placing the appropriate library symbol. For example, IFD is the basic input flip-flop (rising edge triggered), and ILD is the basic input latch (transparent-High). Variations with inverted clocks are also available. The clock ...
Page 8
Spartan and Spartan-XL Families Field Programmable Gate Arrays Table 4: Supported Sources for Spartan/XL Inputs Spartan Inputs 5V, Source TTL Any device 3.3V, CC CMOS outputs Spartan family 5V, CC TTL outputs Any device ...
Page 9
R Output Multiplexer/2-Input Function Generator (Spartan-XL only) The output path in the Spartan-XL IOB contains an addi- tional multiplexer not available in the Spartan IOB. The mul- tiplexer can also be configured as a 2-input function generator, implementing a pass ...
Page 10
Spartan and Spartan-XL Families Field Programmable Gate Arrays Over Operating Conditions" on page makes them unsuitable as wired-AND pull-up resistors. Table 7: Supported Destinations for Spartan/XL Outputs Spartan-XL Outputs Destination 3.3V, CMOS Any device 3.3V, CC CMOS-threshold inputs ...
Page 11
R PSM PSM 2 Doubles Figure 8: Spartan/XL CLB Routing Channels and Interface Block Diagram CLB Interface A block diagram of the CLB interface signals is shown in Figure 9. The input signals to the CLB are distributed evenly on ...
Page 12
Spartan and Spartan-XL Families Field Programmable Gate Arrays Double-Length Lines The double-length lines consist of a grid of metal segments, each twice as long as the single-length lines: they run past two CLBs before entering a PSM. Double-length lines are ...
Page 13
R BUFGS PGCK1 SGCK1 BUFGP 4 IOB locals Any BUFGS X4 locals One BUFGP per Global Line IOB BUFGS PGCK2 SGCK2 BUFGP Figure 11: 5V Spartan Family Global Net Distribution The four Primary Global buffers offer the shortest delay and ...
Page 14
Spartan and Spartan-XL Families Field Programmable Gate Arrays • The single-port configuration contains a RAM array with 16 locations, each one-bit wide. One 4-bit address decoder determines the RAM location for write and read operations. There is ...
Page 15
R WCLK (K) T WSS WE T DSS DATA IN T ASS ADDRESS T ILO DATA OUT Figure 13: Data Write and Access Timing for RAM WCLK can be configured as active on either the rising edge (default) or the ...
Page 16
Spartan and Spartan-XL Families Field Programmable Gate Arrays CLB signals from which they are originally derived are shown in Table 10. Table 10: Dual-Port RAM Signals RAM Signal Function D Data In A[3:0] Read Address for Single-Port. Write Address for ...
Page 17
R and Spartan-XL families, speeding up arithmetic and count- ing functions. The carry chain in 5V Spartan devices can run either up or down. At the top and bottom of the columns where there are no CLBs above and below, ...
Page 18
Spartan and Spartan-XL Families Field Programmable Gate Arrays C OUT CARRY LOGIC G CARRY OUT0 H1 F CARRY Figure 16: Fast Carry Logic in Spartan/XL CLB ...
Page 19
Figure 17: Detail of Spartan/XL Dedicated Carry Logic 3-State Long Line Drivers A pair of 3-state buffers is associated with each CLB in the array. These 3-state buffers (BUFT) ...
Page 20
Spartan and Spartan-XL Families Field Programmable Gate Arrays On-Chip Oscillator Spartan/XL devices include an internal oscillator. This oscil- lator is used to clock the power-on time-out, for configura- tion memory clearing, and as the source of CCLK in Master configuration ...
Page 21
R Figure diagram of the Spartan/XL boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. Spartan/XL devices can also be configured ...
Page 22
Spartan and Spartan-XL Families Field Programmable Gate Arrays IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB BYPASS REGISTER INSTRUCTION REGISTER TDI 22 DATA IN IOB.T IOB IOB IOB IOB IOB.I IOB IOB IOB IOB.Q IOB IOB.T M ...
Page 23
R Table 12: Boundary Scan Instructions Instruction Test Selected EXTEST SAMPLE/ PRELOAD USER USER READBACK CONFIGURE 1 ...
Page 24
... The IDCODE register has the following binary format: vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1 where c = the company code (49h for Xilinx the array dimension in CLBs (ranges from 0Ah for XCS05XL to 1Ch for XCS40XL the family code (02h for Spartan-XL family the die version number (currently 0h) Table 13: IDCODEs Assigned to Spartan-XL FPGAs FPGA ...
Page 25
R PWRDWN Outputs Power-down retains the configuration, but loses all data stored in the device flip-flops. All inputs are interpreted as Low, but the internal combinatorial logic is fully functional. Make sure that the combination of all inputs Low and ...
Page 26
Spartan and Spartan-XL Families Field Programmable Gate Arrays During configuration, some of the I/O pins are used tempo- rarily for the configuration process. All pins used during con- figuration are shown in Table 14 and Table 14: Pin Functions During ...
Page 27
R Master Serial Mode The Master serial mode uses an internal oscillator to gener- ate a Configuration Clock (CCLK) for driving potential slave devices and the Xilinx serial-configuration (SPROM). The CCLK speed is selectable as either 1 MHz (default) or ...
Page 28
Spartan and Spartan-XL Families Field Programmable Gate Arrays Slave Serial is the default mode if the Mode pins are left unconnected, as they have weak pull-up resistors during configuration. Multiple slave devices with identical configurations can be wired with parallel ...
Page 29
R DIN T DCC CCLK DOUT (Output) Symbol T DCC T CCD T CCO T CCH T CCL F CC Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High. Figure 26: Slave Serial ...
Page 30
Spartan and Spartan-XL Families Field Programmable Gate Arrays after the DONE pin for that device goes High. (The exact timing is determined by development system options.) Since the DONE pin is open-drain and does not drive a High value, tying ...
Page 31
R CCLK T IC INIT D0-D7 DOUT Symbol CCLK T CCH T CCL F CC Notes: If not driven by the preceding DOUT, CS1 must remain High until the 1. device is fully configured. ...
Page 32
Spartan and Spartan-XL Families Field Programmable Gate Arrays Table 16: Spartan/XL Data Stream Formats Serial Modes Data Type (D0...) Fill Byte 11111111b Preamble Code 0010b Length Count COUNT[23:0] Fill Bits 1111b Field Check - Code Start Field 0b Data Frame ...
Page 33
... However, the Length Count value must be adjusted for all such extra "one" bits, even for extra leading ones at the beginning of the header. 3. Express mode adds 57 (XCS05XL, XCS10XL (XCS20XL, XCS30XL, XCS40XL) bits per frame, + additional start-up bits. During Readback, 11 bits of the 16-bit checksum are added to the end of the Readback data stream. The checksum is ...
Page 34
Spartan and Spartan-XL Families Field Programmable Gate Arrays LAST DATA FRAME Configuration Sequence There are four major steps in the Spartan/XL power-up con- figuration sequence. • Configuration Memory Clear • Initialization • Configuration • ...
Page 35
Boundary Scan Valid Instructions Available: Yes Test MODE, Generate One Time-Out Pulse Keep Clearing Configuration Memory EXTEST* SAMPLE/PRELOAD Completely Clear BYPASS Configuration Memory CONFIGURE* Once More (* if PROGRAM = High) ...
Page 36
Spartan and Spartan-XL Families Field Programmable Gate Arrays For more details on Configuration, refer to the Xilinx Appli- cation Note "FPGA Configuration Guidelines" (XAPP090). Start-Up Start-up is the transition from the configuration process to the intended user operation. This transition ...
Page 37
R Length Count Match CCLK DONE I/O CCLK_NOSYNC GSR Active DONE I/O CCLK_SYNC GSR Active DONE I/O UCLK_NOSYNC GSR Active DONE I/O UCLK_SYNC GSR Active Synchronization Uncertainty Configuration Through the Boundary Scan Pins Spartan/XL devices can be configured through the ...
Page 38
Spartan and Spartan-XL Families Field Programmable Gate Arrays Readback The user can read back the content of configuration mem- ory and the level of certain internal nodes without interfering with the normal operation of the device. Readback not only reports ...
Page 39
R Readback Abort When the Readback Abort option is selected, a High-to-Low transition on RDBK.TRIG terminates the Readback opera- tion and prepares the logic to accept another trigger. After an aborted Readback, additional clocks (up to one Readback clock per ...
Page 40
Spartan and Spartan-XL Families Field Programmable Gate Arrays Readback Switching Charateristics Guidelines The following guidelines reflect worst-case values over the recommended operating conditions. Finished Internal Net rdbk.TRIG T RTRC rdclk.I T RCL rdbk.RIP rdbk.DATA DUMMY Figure 33: Spartan and Spartan-XL ...
Page 41
R Configuration Switching Characteristics PROGRAM INIT CCLK Output or Input Master Mode Symbol Description T Power-on reset POR T Program Latency PI T CCLK (output) delay ICCK T CCLK (output) period, slow CCLK T CCLK (output) period, ...
Page 42
Spartan and Spartan-XL Families Field Programmable Gate Arrays Spartan Detailed Specifications Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or ...
Page 43
... CMOS outputs - 0.4 3.0 Commercial - 3.0 Industrial - 6.0 –10 +10 - 0.02 0.25 0.02 or GND, and the FPGA configured with a Tie CC Speed Grade -4 -3 Device Max Max XCS05 2.0 4.0 XCS10 2.4 4.3 XCS20 2.8 5.4 XCS30 3.2 5.8 XCS40 3.5 6.4 XCS05 2.5 4.4 XCS10 2.9 4.7 XCS20 3.3 5.8 XCS30 3.6 6.2 XCS40 3.9 6.7 Units - Units ...
Page 44
Spartan and Spartan-XL Families Field Programmable Gate Arrays Spartan CLB Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test ...
Page 45
R Spartan CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are ...
Page 46
Spartan and Spartan-XL Families Field Programmable Gate Arrays Spartan CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (continued) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived ...
Page 47
... Device Max Max XCS05 5.3 8.7 XCS10 5.7 9.1 XCS20 6.1 9.3 XCS30 6.5 9.4 XCS40 6.8 10.2 XCS05 9.0 11.5 XCS10 9.4 12.0 XCS20 9.8 12.2 XCS30 10.2 12.8 XCS40 10.5 12.8 XCS05 5.8 9.2 XCS10 6.2 9.6 XCS20 6.6 9.8 XCS30 7.0 9.9 XCS40 7.3 10.7 XCS05 9.5 12.0 XCS10 9.9 12.5 XCS20 10.3 12.7 XCS30 10.7 13.2 XCS40 11.0 14.3 All devices 0.8 1.0 All devices 1.5 2.0 Figure 33. Units ...
Page 48
Spartan and Spartan-XL Families Field Programmable Gate Arrays Capacitive Load Factor Figure 33 shows the relationship between I/O output delay and load capacitance. It allows a user to adjust the specified output delay if the load capacitance is different than ...
Page 49
... Description www.xilinx.com 1-800-255-7778 Speed Grade -4 -3 Device Min Min XCS05 1.2 / 1.7 1.8 / 2.5 XCS10 1.0 / 2.3 1.5 / 3.4 XCS20 0.8 / 2.7 1.2 / 4.0 XCS30 0.6 / 3.0 0.9 / 4.5 XCS40 0.4 / 3.5 0.6 / 5.2 XCS05 4.3 / 0.0 6.0 / 0.0 XCS10 4.3 / 0.0 6.0 / 0.0 XCS20 4.3 / 0.0 6.0 / 0.0 XCS30 4.3 / 0.0 6.0 / 0.0 XCS40 5.3 / 0.0 6.8 / 0.0 XCS05 0.9 / 2.2 1.5 / 3.0 XCS10 0.7 / 2.8 1.2 / 3.9 XCS20 0.5 / 3.2 0.9 / 4.5 XCS30 0.3 / 3.5 0.6 / 5.0 XCS40 0.1 / 4.0 0.3 / 5.7 XCS05 4.0 / 0.0 5.7 / 0.0 XCS10 4.0 / 0.0 5.7 / 0.0 XCS20 4.0 / 0.5 5.7 / 0.5 XCS30 4.0 / 0.5 5.7 / 0.5 XCS40 5.0 / 0.0 6.5 / 0.0 Units ...
Page 50
... Device Min All devices 1.6 All devices 1.5 All devices 0.0 All devices 0.0 All devices - All devices - All devices - All devices - XCS05 3.6 XCS10 3.7 XCS20 3.8 XCS30 4.5 XCS40 5.5 All devices 11.5 XCS05 - XCS10 - XCS20 - XCS30 - XCS40 - www.xilinx.com 1-800-255-7778 R Speed Grade -4 -3 Max Min Max Units - 2 2 0.9 - ...
Page 51
... All devices All devices All devices All devices All devices All devices All devices All devices All devices All devices XCS05 XCS10 XCS20 XCS30 XCS40 threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output CC www.xilinx.com 1-800-255-7778 Speed Grade ...
Page 52
Spartan and Spartan-XL Families Field Programmable Gate Arrays Spartan-XL Detailed Specifications Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or ...
Page 53
R Spartan-XL DC Characteristics Over Operating Conditions Symbol V High-level output voltage @ I OH High-level output voltage @ I V Low-level output voltage @ I OL Low-level output voltage @ I Low-level output voltage @ I V Data retention ...
Page 54
... These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Description www.xilinx.com 1-800-255-7778 Speed Grade -5 -4 Device Max Max XCS05XL 1.4 1.5 XCS10XL 1.7 1.8 XCS20XL 2.0 2.1 XCS30XL 2.3 2.5 XCS40XL 2 ...
Page 55
R Spartan-XL CLB Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For ...
Page 56
Spartan and Spartan-XL Families Field Programmable Gate Arrays Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from ...
Page 57
R Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (cont.) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below ...
Page 58
... Listed below are representative values for typical pin locations and normal clock loading. Description threshold with 50 pF external capacitive load. CC www.xilinx.com 1-800-255-7778 Speed Grade -5 -4 Device Max Max XCS05XL 4.6 5.2 XCS10XL 4.9 5.5 XCS20XL 5.2 5.8 XCS30XL 5.5 6.2 XCS40XL 5.8 6.5 All Devices 1 ...
Page 59
... Spartan and Spartan-XL Families Field Programmable Gate Arrays and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. Description XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL ...
Page 60
... Device Min All devices 0.0 All devices 1.0 All devices 0.7 All devices 0.0 All devices - All devices - All devices - All devices - XCS05XL 4.0 XCS10XL 4.8 XCS20XL 5.0 XCS30XL 5.5 XCS40XL 6.5 All devices 10.5 XCS05XL - XCS10XL - XCS20XL - XCS30XL - XCS40XL - www.xilinx.com 1-800-255-7778 R Speed Grade -5 -4 Max Min Max Units - 0 1 0.8 - ...
Page 61
... All devices All devices All devices All devices All devices All devices All devices All devices All devices All devices XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output CC www.xilinx.com 1-800-255-7778 Speed Grade ...
Page 62
Spartan and Spartan-XL Families Field Programmable Gate Arrays Pin Descriptions There are three types of pins in the Spartan/XL devices: • Permanently dedicated pins • User I/O pins that can have special functions • Unrestricted user-programmable I/O pins. Before and ...
Page 63
R Table 18: Pin Descriptions (Continued) I/O During I/O After Pin Name Config. Config. PWRDWN I I User I/O Pins That Can Have Special Functions TDO O O TDI, TCK, I I/O TMS or I (JTAG) HDC O I/O LDC ...
Page 64
Spartan and Spartan-XL Families Field Programmable Gate Arrays Table 18: Pin Descriptions (Continued) I/O During I/O After Pin Name Config. Config. SGCK1 - Weak I or I/O SGCK4 Pull-up (Spartan) (except SGCK4 is DOUT) GCK1 - Weak I or I/O ...
Page 65
... M0 P32 VCC P33 (1) Not Connected , P34 (2) PWRDWN (1) (2) I/O, PGCK2 , GCK3 P35 DS060 (v1.6) September 19, 2001 Product Specification Spartan and Spartan-XL Families Field Programmable Gate Arrays XCS05 and XCS05XL Device Pinouts XCS05/XL Pad Name I/O (HDC) I/O I/O (LDC) I/O I/O Bndry I/O VQ100 Scan I/O P89 - I/O P90 32 I/O (INIT) ...
Page 66
... Notes Spartan only 2. 3V Spartan-XL only 3. The “PWRDWN” on the XCS05XL is not part of the Boundary Scan chain. For the XCS05XL, subtract 1 from all Boundary Scan numbers from GCK3 on (127 and higher). XCS10 and XCS10XL Device Pinouts XCS10/XL Pad Name PC84 VQ100 CS144 ...
Page 67
R XCS10 and XCS10XL Device Pinouts XCS10/XL Pad Name PC84 VQ100 CS144 I/O, P35 P27 (1) PGCK2 (2) GCK3 I/O (HDC) P36 P28 I I I/O - P29 I/O (LDC) P37 P30 GND - - I/O ...
Page 68
Spartan and Spartan-XL Families Field Programmable Gate Arrays XCS10 and XCS10XL Device Pinouts XCS10/XL Pad Name PC84 VQ100 CS144 I/O - P85 I/O P83 P86 I/O P84 P87 GND P1 P88 Notes Spartan only 2. 3V Spartan-XL only ...
Page 69
R XCS20 and XCS20XL Device Pinouts XCS20/XL (2) Pad Name VQ100 CS144 TQ144 I I (2) VCC - - I/O P16 H3 I/O P17 GND - J3 I/O - ...
Page 70
Spartan and Spartan-XL Families Field Programmable Gate Arrays XCS20 and XCS20XL Device Pinouts XCS20/XL (2) Pad Name VQ100 CS144 TQ144 GND - J10 I/O - J11 I/O - J12 (2) VCC ...
Page 71
R XCS30 and XCS30XL Device Pinouts XCS30/XL Pad Name VQ100 VCC P89 I/O P90 I/O P91 I/O P92 I/O P93 I/O - I/O - I/O P94 I/O P95 VCC - I/O - I/O - I/O - I/O - GND - ...
Page 72
Spartan and Spartan-XL Families Field Programmable Gate Arrays XCS30 and XCS30XL Device Pinouts (Continued) XCS30/XL Pad Name VQ100 I/O, TMS P6 I/O P7 VCC - I/O - I/O - I/O - I/O - I/O - I/O P8 I/O P9 I/O ...
Page 73
R XCS30 and XCS30XL Device Pinouts (Continued) XCS30/XL Pad Name VQ100 (1) (2) I/O, PGCK2 , GCK3 P27 I/O (HDC) P28 I/O - I/O - I/O P29 I/O (LDC) P30 I/O - I/O - I/O - I/O - I/O - ...
Page 74
Spartan and Spartan-XL Families Field Programmable Gate Arrays XCS30 and XCS30XL Device Pinouts (Continued) XCS30/XL Pad Name VQ100 I/O - I/O - I/O - I/O P45 I/O P46 I/O - I/O - I/O P47 (1) (2) I/O, SGCK3 , GCK4 ...
Page 75
R XCS30 and XCS30XL Device Pinouts (Continued) XCS30/XL Pad Name VQ100 I/O - I/O - (2) I/O (D2 ) P68 I/O P69 VCC - I/O - I/O - I/O - I/O - GND - I/O - I/O - I/O - ...
Page 76
Spartan and Spartan-XL Families Field Programmable Gate Arrays XCS30 and XCS30XL Device Pinouts (Continued) XCS30/XL Pad Name VQ100 I/O P83 I/O - I/O - I/O P84 I/O P85 I/O P86 I/O P87 GND P88 2/8/00 Notes Spartan only ...
Page 77
R XCS40 and XCS40XL Device Pinouts XCS40/XL Pad Name PQ208 PQ240 BG256 VCC P183 P212 VCC I/O P184 P213 C10 I/O P185 P214 D10 I/O P186 P215 A9 I/O P187 P216 B9 I/O P188 P217 C9 I/O P189 P218 D9 ...
Page 78
Spartan and Spartan-XL Families Field Programmable Gate Arrays XCS40 and XCS40XL Device Pinouts XCS40/XL Pad Name PQ208 PQ240 BG256 I I I/O P44 P52 V1 I/O P45 P53 T4 I/O P46 P54 U3 I/O P47 P55 ...
Page 79
R XCS40 and XCS40XL Device Pinouts XCS40/XL Pad Name PQ208 PQ240 BG256 I/O, P108 P124 U18 (1) PGCK3 , (2) GCK5 I/O P109 P125 T17 I/O P110 P126 V20 I/O - P127 U20 I/O P111 P128 T18 I ...
Page 80
Spartan and Spartan-XL Families Field Programmable Gate Arrays XCS40 and XCS40XL Device Pinouts XCS40/XL Pad Name PQ208 PQ240 BG256 I A13 I D12 I/O P174 P202 C12 I/O P175 P203 B12 I/O P176 P205 A12 I/O ...
Page 81
... Table 20: User I/O Chart for Spartan/XL FPGAs Max Device I/O PC84 XCS05 80 61 XCS10 112 61 XCS20 160 - XCS30 192 - XCS40 224 - XCS05XL 80 61 XCS10XL 112 61 XCS20XL 160 - XCS30XL 192 - XCS40XL 224 - 5/19/99 DS060 (v1.6) September 19, 2001 Product Specification Spartan and Spartan-XL Families Field Programmable Gate Arrays Table 20 ...
Page 82
Spartan and Spartan-XL Families Field Programmable Gate Arrays Ordering Information Example: XCS20XL-4 PQ208C Device Type Speed Grade - Ball Grid Array PC = Plastic Lead Chip Carrier PQ = Plastic Quad Flat Pack Revision History The ...