XCS05-3BG100C XILINX [Xilinx, Inc], XCS05-3BG100C Datasheet - Page 31

• Manufacturer Part Number: XCS05-3BG100C
• Description: Spartan and Spartan-XL Families Field Programmable Gate Arrays
• Manufacturer: XILINX [Xilinx, Inc]

Setting CCLK Frequency
In Master mode, CCLK can be generated in either of two
frequencies. In the default slow mode, the frequency ranges
from 0.5 MHz to 1.25 MHz for Spartan/XL devices. In fast
CCLK mode, the frequency ranges from 4 MHz to 10 MHz
for Spartan/XL devices. The frequency is changed to fast by
an option when running the bitstream generation software.
Data Stream Format
The data stream ("bitstream") format is identical for both
serial configuration modes, but different for the Spartan-XL
Express mode. In Express mode, the device becomes
active when DONE goes High, therefore no length count is
required. Additionally, CRC error checking is not supported
in Express mode. The data stream format is shown in
DS060 (v1.6) September 19, 2001
Product Specification
D0-D7
DOUT
CCLK
INIT
R
Notes:
1.
Symbol
T
T
T
T
F
If not driven by the preceding DOUT, CS1 must remain High until the
device is fully configured.
T
CCH
CCL
DC
CD
CC
IC
Figure 28: Express Mode Programming Switching Characteristics
T
IC
CCLK
T
DC
INIT (High) setup time
D0-D7 setup time
D0-D7 hold time
CCLK High time
CCLK Low time
CCLK Frequency
BYTE
0
Description
Header Received
Spartan and Spartan-XL Families Field Programmable Gate Arrays
BYTE
www.xilinx.com
1-800-255-7778
1
Table
mode data is shown with D0 at the left and D7 at the right.
The configuration data stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator field of ones (or 24 fill bits, in Spartan-XL
Express mode). This header is followed by the actual con-
figuration data in frames. The length and number of frames
depends on the device type (see
begins with a start field and ends with an error check. In
serial modes, a postamble code is required to signal the end
of data for a single device. In all cases, additional start-up
bytes of data are required to provide four clocks for the star-
tup sequence at the end of configuration. Long daisy chains
require additional startup bytes to shift the last data through
the chain. All start-up bytes are "don’t cares".
T
CD
16. Bit-serial data is read from left to right. Express
Min
20
45
45
BYTE
5
0
-
6
Max
10
-
-
-
-
-
Units
MHz
ns
ns
ns
ns
s
Table
FPGA Filled
17).
DS060_28_080400
Each frame
31