MK61FN1M0VMD12 FREESCALE [Freescale Semiconductor, Inc], MK61FN1M0VMD12 Datasheet - Page 41

• Manufacturer Part Number: MK61FN1M0VMD12
• Description: K61 Sub-Family Data Sheet
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

6.4.4 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Freescale Semiconductor, Inc.
Num
FB1
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
Operating voltage
Frequency of operation
Clock period
Description
Table 25. Flexbus limited voltage range switching specifications
Figure 14. Read data latch cycle timing in non-fast mode
Figure 15. Read data latch cycle timing in fast mode
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
tRR
tRR
Table continues on the next page...
tRP
tRP
tRC
tRC
data
Preliminary
tIS
tREH
tREH
data
tIS
data
data
Peripheral operating requirements and behaviors
Min.
2.7
20
—
data
tCH
FB_CLK
data
Max.
3.6
—
tCH
MHz
Unit
ns
V
Notes
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