MK61FN1M0VMD12 FREESCALE [Freescale Semiconductor, Inc], MK61FN1M0VMD12 Datasheet - Page 61

• Manufacturer Part Number: MK61FN1M0VMD12
• Description: K61 Sub-Family Data Sheet
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

6.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
6.8.1.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Freescale Semiconductor, Inc.
Symbol
MII1
MII2
MII3
MII4
MII5
MII6
MII7
MII8
—
—
RXCLK frequency
RXCLK pulse width high
RXCLK pulse width low
RXD[3:0], RXDV, RXER to RXCLK setup
RXCLK to RXD[3:0], RXDV, RXER hold
TXCLK frequency
TXCLK pulse width high
TXCLK pulse width low
TXCLK to TXD[3:0], TXEN, TXER invalid
TXCLK to TXD[3:0], TXEN, TXER valid
Description
TXCLK (input)
TXD[n:0]
TXEN
TXER
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Figure 25. MII transmit signal timing diagram
Table 39. MII signal switching specifications
MII8
Preliminary
MII6
Valid data
Valid data
Valid data
MII5
MII7
Peripheral operating requirements and behaviors
35%
35%
35%
35%
Min.
—
—
—
5
5
2
Max.
65%
65%
65%
65%
25
25
25
—
—
—
RXCLK
RXCLK
TXCLK
TXCLK
period
period
period
period
MHz
MHz
Unit
ns
ns
ns
ns
61