MK61FX512VMD12 FREESCALE [Freescale Semiconductor, Inc], MK61FX512VMD12 Datasheet - Page 40

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MK61FX512VMD12

Manufacturer Part Number
MK61FX512VMD12
Description
K61 Sub-Family
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Peripheral operating requirements and behaviors
6.4.3 NFC specifications
The NAND flash controller (NFC) implements the interface to standard NAND flash
memory devices. This section describes the timing parameters of the NFC.
In the following table:
40
• T
• T
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
EP1a
Num
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
H
L
is flash clock low time,
is the flash clock high time and
EZP_CK frequency of operation (all commands except
READ)
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Description
Table 24. EzPort switching specifications (continued)
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
EP3
Figure 11. EzPort Timing Diagram
EP5
EP6
EP7
EP4
EP8
EP9
EP2
2 x t
Min.
EZP_CK
5
5
2
5
0
Freescale Semiconductor, Inc.
f
f
Max.
SYS
SYS
16
12
/2
/8
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns

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