MK61FX512VMD12 FREESCALE [Freescale Semiconductor, Inc], MK61FX512VMD12 Datasheet - Page 71

• Manufacturer Part Number: MK61FX512VMD12
• Description: K61 Sub-Family
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

6.8.12 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
6.8.12.1 Normal Run, Wait and Stop mode performance over a limited
This section provides the operating performance over a limited operating voltage for the
device in Normal Run, Wait and Stop modes.
Freescale Semiconductor, Inc.
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
Num.
Table 50. I2S/SAI master mode timing in Normal Run, Wait and Stop modes
Operating voltage
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
operating voltage range
(limited voltage range)
Characteristic
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
2.7
40
45%
80
45%
—
0
—
0
15
0
Peripheral operating requirements and behaviors
Min.
3.6
—
55%
—
55%
15
—
15
—
—
—
Max.
V
ns
MCLK period
ns
BCLK period
ns
ns
ns
ns
ns
ns
Unit
71