CY8C201A0_12 CYPRESS [Cypress Semiconductor], CY8C201A0_12 Datasheet - Page 7

• Manufacturer Part Number: CY8C201A0_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

I
The CapSense Express devices support the industry standard I
■
■
■
■
The I
I
The device uses a seven bit addressing protocol. The I
the first 7 bit contains address and the last LSB indicates the data transfer direction. Zero in the LSB bit indicates the write transaction
form master and one indicates read transfer by the master. The following table shows the example for different I
Table 1. I
I
‘Clock stretching’ or ‘bus stalling’ in I
is a state in which the slave holds the SCL line low to indicate
that it is busy. In this condition, the master is expected to wait till
the SCL is released by the slave.
When an I
device, the CapSense Express stalls the I
reception of each byte (that is, just before the ACK/NAK bit) until
processing of the byte is complete and critical internal functions
are executed. It is recommended to use a fully I
master to communicate with CapSense Express device.
Document Number: 001-54607 Rev. *G
2
2
2
C Device Addressing
C Clock Stretching
Configuring the device
Reading the status and data registers of the device
To control the device operation
Executing commands
C Interface
7 Bit Slave Address
2
C address can be modified during configuration.
2
2
C master communicates with the CapSense Express
C Address Examples
75
75
1
1
D7
0
0
1
1
2
C communication protocol
D6
0
0
0
0
2
C bus after the
2
D5
C compliant
0
0
0
0
2
C data transfer is always initiated by the master sending one byte address;
D4
0
0
1
1
2
C protocol, which can be used for:
If an I
software I
of time (specified in
8) for each register write and read operation before the next bit
is transmitted. Check the SCL status (should be high) before I
master initiates any data transfer with CapSense Express. If the
master fails to do so and continues to communicate, the
communication is incorrect.
The following diagrams represent the ACK time delays shown in
Format for Register Write and Read on page 8
D3
0
0
0
0
2
C master does not support clock stretching (a bit banged
D2
2
0
0
1
1
C master), the master must wait for a specific amount
D1
1
1
1
1
Format for Register Write and Read on page
0(W)
0(W)
1(W)
1(R)
D0
8 Bit Slave Address
CY8C201A0
2
C addresses.
for write and read.
02
03
96
97
Page 7 of 38
2
C