Z86130 ZILOG [Zilog, Inc.], Z86130 Datasheet - Page 19

• Manufacturer Part Number: Z86130
• Description: NTSC LINE 21 DECIDER
• Manufacturer: ZILOG [Zilog, Inc.]

SERIAL COMMUNICATIONS INTERFACE
Commands and data are sent to and from the Z86129
through its serial communications interface. Two Serial
Control Modes are available. One mode is a two wire I
bus interface. The other serial mode is a three wire,
synchronous serial peripheral interface (SPI). In both
cases the Z86129/130/131 acts as a slave device.
This port is the path for setting the configuration and
operational modes of the device. It is also the port for
outputting the recovered XDS data and for inputting the
OSD data for display.
Five pins are dedicated to the control port function and one
additional pin can be configured to provide an interrupt
output. These pins are designated as shown in Table 5.
Signal
Pin #
I/O
I2C
SPI
Notes:
SMS = Serial Mode Select High = SPI & Low =
SCK = Serial port clock for either Serial Mode.
SDA = Serial port data for
SDO = Serial Data Out for SPI Mode. Not used in
SEN = SPI Mode Enable signal. Must be High for
When the Vertical Lock = VIDEO, the VIN/INTRO (pin13)
is configured as an output, providing the INTRO signal.
This interrupt operation is available in either serial control
mode.
The Z86129/130/131 is able to interrupt on the occurrence
of any of several events. The master device will clear the
interrupt by writing to the Interrupt Request Register.
I
The serial control mode in use is selected by the state of
the SMS pin. When SMS is set Low, the Z86129/130/131
will be in the I
supports a bidirectional two wire bus and data
transmission protocol. The bus is controlled by the master
device, which generates the serial clock (SCK), controls
the bus access and generates the Start and Stop
conditions. The SDA pin is the bidirectional Data line. In
this mode the SDO output is not used and the pin will be in
its high impedance state.
DS96TEL0200
2
C Bus Operation
Table 5. Z86129/130/131 Serial Control Signals
SMS
6
0
1
I
2
C mode. In this mode, the Z86129 also
SCK
CLK
CLK
15
I
I
2
C
Data In
Mode and Data In for SPI Mode.
SDA
Data
I/O
14
Data Out
SDO
Hi-Z
16
O
I
2
C
I
I
2
2
C
C
Enable
Mode.
P R E L I M I N A R Y
Mode.
SEN
4
1
I
2
C
The Z86129/130/131 can receive or transmit data under
control of the master device. The Z86129/130/131 is a
slave device. Communication is initiated when the master
device sends the start condition followed by the
Z86129/130/131 Slave Address Read byte (29h) or Slave
Address Write byte (28h). The Z86129/130/131 will
respond with an Acknowledge. The I
Least Significant Bit (LSB) of the I
below in Table 6.
Note: When the SMS and SEN pins are both Low, the part will
be in the RESET state. Therefore the SEN pin can be used to
reset the part while in the I
to an NRESET signal or tied High if no reset is desired.
The I
1. Data transfer can only be started when the bus is not
2. During data transfer, data transitions must not occur
Bus Conditions are Defined as:
Not Busy: Data and Clock lines both High.
Start: A High to Low transition of SDA line while SCK line
is High.
Stop: A Low to High transition of SDA line while SCK line
is High.
Acknowledge: When addressed, the receiving device
must output an acknowledge after the reception of each
byte. The master device must generate the clock for the
acknowledge
Acknowledge (NACK) is SDA=High.
Data: The data (SDA) is output by the transmitting device
on the falling edge of SCK, MSB first. The receiving device
will read the data, MSB first, on the rising edge of SCK.
Communication with the Z86129/130/131 is initiated when
the master device sends the Z86129/130/131 slave
address following a start condition. The Z86129/130/131
has a preset, single, seven-bit slave address. The Z86129
will respond with an acknowledge. The eighth bit of the
slave address is driven High for Read operations and Low
for Write operations.
I
2
busy.
while the clock is High.
C Address
Table 6. Z86129/130/131 I
2
C Bus Protocol
bit.
Acknowledge
2
C mode. The SEN pin may be tied
READ
29h
2
C Slave Addresses
NTSC Line 21 Decoder
2
is
2
C RD/nWR bit is the
C addresses listed
SDA=Low.
Z86129/130/131
WRITE
28h
Not
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