Z86130 ZILOG [Zilog, Inc.], Z86130 Datasheet - Page 21

• Manufacturer Part Number: Z86130
• Description: NTSC LINE 21 DECIDER
• Manufacturer: ZILOG [Zilog, Inc.]

The master's sequence for reading two data bytes (total
of three bytes including SSB) from the Z86129/130/131 is
given as:
Start-Slave Address Read/Slave ACK-SS Byte/Master
ACK-Byte (slave)/Master ACK-Byte (slave)/Master NACK-
Stop
Clock and Data Transitions. The SCK and SDA bus lines
are normally pulled High with a resistor. Data on the SDA
bus may only change during SCK Low time periods. Data
changes during SCK High periods will indicate a start or
stop condition as defined in Table 7.
DS96TEL0200
I 2 C-One Byte Write (Status Only)
Note: In all I
from the Z86129/130/131 must be acknowledged by the master
with a NACK (Not ACKnowledge).
I 2 C-Two Byte Read (Status & Data1)
I 2 C-Three Byte Read (Status, Data1, & Data2)
Symbol
t
t
t
t
t
SU.STO
HD.STA
SU.STA
HD.DAT
SU.DAT
t
f
t
t
LOW
t
SCK
High
t
BUF
t
DH
t
AA
t
R
F
Figure 10. I
I
STRT
STRT
STRT
2
C Read operations defined herein, the last byte read
(READ=29h)
SLAVE
ADDR
(READ=29h)
(READ=29h)
Parameter
Clock Frequency
Clock Pulse Width Low
Clock Pulse Width High
SDA and SCL Rise Time
SDA and SCL Fall Time
Clock Low to Data Out Valid
Bus Free Time
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Stop Set-up Time
Data Out Hold Time
Input Filter Time Constant
SLAVE
SLAVE
ADDR
ADDR
2
C Bus READ (Command)
STATUS
SERIAL
(SSB)
STATUS
STATUS
SERIAL
SERIAL
(SSB)
(SSB)
DATA1
READ
NACK
STOP
NACK
READ
DATA1
Table 7. I
DATA2
READ
STOP
NACK
P R E L I M I N A R Y
2
STOP
C Serial Timing Min/max
Start Condition. A High-to-Low transition of SDA with
SCK High is a start condition which must precede any
other command.
Stop Condition. A Low-to-High transition of SDA with
SCK High is a stop condition which terminates all
communications.
Acknowledge. All address and data words are serially
transmitted to and from the Z86129/130/131 in eight bit
words. A ninth bit time is used for the acknowledge. The
acknowledging device does so by pulling the SDA bus Low
during the ninth bit. A Not Acknowledge (NACK) is given
by SDA=High during the ninth clock time.
SDA (IN)
SDA (OUT)
SCK
Min
250
100
4.7
4.0
0.1
4.7
4.0
4.7
4.7
–
–
0
t
SU.STA
t
HD.STA
t
AA
Figure 11. I
t
F
t
HD.DAT
Max
100
300
100
1.0
3.5
t
High
–
–
–
–
–
–
–
–
–
2
C Serial Timing
t
Low
NTSC Line 21 Decoder
t
t
SU.DAT
DH
Z86129/130/131
Units
kHz
ns
ns
ns
ns
t
s
s
s
s
s
s
s
s
s
R
t
BUF
t
SU.STO
21
1