Z86130 ZILOG [Zilog, Inc.], Z86130 Datasheet - Page 20

• Manufacturer Part Number: Z86130
• Description: NTSC LINE 21 DECIDER
• Manufacturer: ZILOG [Zilog, Inc.]

Z86129/130/131
NTSC Line 21 Decoder
SERIAL COMMUNICATIONS INTERFACE (Continued)
Writing to the I
All write commands are either one or two byte commands.
The Z86129/130/131 is enabled when a Start condition
followed by its Slave Address Write byte is received. It will
be disabled once it deems the command to have been
completed or by a Stop condition. A new Start condition
without a Stop condition will begin a new sequence.
Therefore, successive commands may be executed by
successive strings of “Start-Slave Address-Command”
sequences without any intervening Stop condition being
sent.
Notes:
The number of data bytes to be received by the
Z86129/130/131 is inherent in the command and the
Z86129/130/131 will respond with the acknowledge signal
only for the number of bytes expected. If the master writes
more bytes than expected, there will be no acknowledge
for the extra bytes.
A write to the Z86129/130/131 should always be preceded
by
Z86129/130/131 is not busy. The Status register data is
output immediately following the reception of the Slave
Address Read. If the RDY bit is set, the master device can
initiate its write sequence, always beginning with the Start
condition. The first byte of a two byte command is always
written first.
An example of the master's sequence for writing a two byte
command (after RDY had been checked) would be:
Start-Slave Address Write/Slave ACK-CMD (master)/
Slave ACK-DATA (master)/Slave ACK-Stop.
20
I 2 C-One Byte Write (Command)
Note: Status Register RDY bit must be read and checked prior to the
STRT condition of either WRITE sequence above. See One Byte
Read (Status Only) in Figure 10 for more information on reading the
Status Register.
I 2 C-Two Byte Write (Command & Data)
executing
Figure 9. I
STRT
STRT
(WRITE=28h)
(WRITE=28h)
a
SLAVE
SLAVE
ADDR
ADDR
2
C Bus
2
Status
C Bus WRITE (Command)
WRITE
WRITE
CMD
CMD
read
to
STOP
WRITE
DATA
verify
that
P R E L I M I N A R Y
STOP
the
Reading Data Using the I
With the exception of the Serial Status (SS) register, which
may be read at any time, each read operation must be set
up before the data can be read from the serial output
registers of the Z86129/130/131. Data is set up for a read
operation either automatically or manually. XDS data
reads are set up automatically upon recovery by setting a
valid XDS FILTER register selection. All other data read
operations must be set up manually using the READ
SELECT commands RDS1 and RDS2. These commands
load the selected data byte or pair of bytes into the serial
output register(s), set the SS register RD2 bit according to
the number of data bytes requested and set the SS
register DAV bit to indicate availability of data.
The Z86129/130/131 I
byte read sequences. All read sequences output the SS
register as the first output byte. If the
is set, a two or three byte read sequence can then be
initiated, beginning with a new STRT condition. If the DAV
bit is not set, the I
read any data bytes or the desired data can be lost from
the Z86129/130/131output registers.
The number of data bytes available is indicated by the
state of the RD2 bit of the serial status. In a typical read
operation the status byte is read and the DAV and RD2 bits
are examined. If one or two data bytes are available they
are read in sequence separated by acknowledges.
Note:
In all I
defined in Figure 10) the last byte read from the
Z86129/130/131 should be acknowledged by the master
with a NACK (Not ACKnowledge). It is also necessary to
read all available data in a read operation to clear the DAV
bit and permit subsequent reads. DAV is cleared by the
master clocking out the eighth bit of the last data-byte
read. DAV is never cleared by just reading the SSB (one-
byte read) alone. All data is output MSB first.
2
C Read operations (one, two, and three byte as
2
C master device should not attempt to
2
C Bus supports one, two and three
2
C Bus
s
erial
DS96TEL0200
s
tatus DAV bit