M24C64-W STMICROELECTRONICS [STMicroelectronics], M24C64-W Datasheet
M24C64-W
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M24C64-W Summary of contents
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... More than 200-year data retention ■ Packages: – RoHS compliant and halogen-free ® (ECOPACK ) August 2012 This is information on a product in full production. M24C64-W M24C64-R M24C64-F 64-Kbit serial I²C bus EEPROM WLCSP (CS) Doc ID 16891 Rev 27 M24C64-DF Datasheet production data TSSOP8 (DW) 169 mil width ...
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... Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.1 2/42 M24C64-W M24C64-R M24C64-F M24C64- Operating supply voltage Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Identification Page (M24C64-D only Lock Identification Page (M24C64-D only ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 18 Minimizing Write delays by polling on ACK ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF 5.2.2 5.2.3 5.3 Read Identification Page (M24C64-D only 5.4 Read the lock status (M24C64-D only Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Doc ID 16891 Rev 27 ...
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... Table 10. Input parameters Table 11. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 12. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 13. DC characteristics (M24C64-W, device grade Table 14. DC characteristics (M24C64-R, device grade Table 15. DC characteristics (M24C64-F, M24C64-DF, device grade Table 16. 400 kHz AC characteristics Table 17. ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. 5-bump WLCSP connections (top view Figure 4. 8-bump thin WLCSP connections (top view Figure 5. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Figure bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Write mode sequences with (data write enabled Figure 9 ...
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... The M24C64 is a 64-Kbit I Memory) organized × 8 bits. The M24C64-W can operate with a supply voltage from 2 5.5 V, the M24C64-R can operate with a supply voltage from 1 5.5 V, and the M24C64-F and M24C64-DF can operate with a supply voltage from 1 5.5 V, over an ambient temperature range of -40 ° ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF Figure 3. 5-bump WLCSP connections (top view) Note: Inputs E2, E1, E0 are internally connected to (001). Please refer to explanations. Figure 4. 8-bump thin WLCSP connections (top view) Caution: As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form or in WLCSP package by STMicroelectronics must never be exposed to UV light ...
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... Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either driven low or left floating. When Write Control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged. 8/42 M24C64-W M24C64-R M24C64-F M24C64- shown in Figure 5. When not connected (left floating), these inputs SS ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF 2.5 V (ground the reference for the V SS 2.6 Supply voltage (V 2.6.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V in Section 8: DC and AC recommended to decouple the 100 nF) close to the V ...
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... Memory organization 3 Memory organization The memory is organized as shown below. Figure 6. Block diagram 10/42 M24C64-W M24C64-R M24C64-F M24C64-DF Doc ID 16891 Rev 27 ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF 4 Device operation The device supports the I data on to the bus is defined transmitter, and any device that reads the data receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization ...
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... Serial Data (SDA) after sending eight bits of data. During the 9 acknowledge the receipt of the eight data bits. 12/42 M24C64-W M24C64-R M24C64-F M24C64-DF th clock pulse period, the receiver pulls Serial Data (SDA) low to Doc ID 16891 Rev 27 ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF 4.5 Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2(on Serial Data (SDA), most significant bit first). ...
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... During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. If the Write Control input (WC) is driven High, the Write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in 14/42 M24C64-W M24C64-R M24C64-F M24C64-DF Figure A13 A12 A11 ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF 5.1.1 Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack ...
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... The transfer is terminated by the bus master generating a Stop condition. Figure 9. Write mode sequences with (data write inhibited) WC Byte Write WC Page Write WC (cont'd) Page Write (cont'd) 16/42 M24C64-W M24C64-R M24C64-F M24C64-DF 9. After each transferred byte, the internal page address counter is ACK Dev sel Byte addr R/W ACK Dev sel Byte addr R/W ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF 5.1.3 Write Identification Page (M24C64-D only) The Identification Page (32 bytes additional page which can be written and (later) permanently locked in Read-only mode written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences: ● ...
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... A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where integer. 18/42 M24C64-W M24C64-R M24C64-F M24C64-DF ( consequence, the maximum cycling budget is Table 11: Cycling performance by groups of four Doc ID 16891 Rev 27 (a) ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF 5.1.6 Minimizing Write delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (t shown in AC characteristics tables in is shorter ...
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... RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. 20/42 M24C64-W M24C64-R M24C64-F M24C64-DF ACK NO ACK Dev sel ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF 5.2.2 Current Address Read For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented ...
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... Initial delivery state 6 Initial delivery state The device is delivered with all the memory array bits set to 1 (each byte contains FFh). 22/42 M24C64-W M24C64-R M24C64-F M24C64-DF Doc ID 16891 Rev 27 ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF 7 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... MHz devices identified by process letter K. Cmax Table 9. AC measurement conditions Symbol C Load capacitance bus SCL input rise/fall time, SDA input fall time Input levels Input and output timing reference levels 24/42 M24C64-W M24C64-R M24C64-F M24C64-DF Parameter Parameter Parameter Parameter Doc ID 16891 Rev 27 Min. Max. Unit 2.5 5.5 V – ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF Figure 12. AC measurement I/O waveform Table 10. Input parameters Symbol C Input capacitance (SDA Input capacitance (other pins Input impedance (E2, E1, E0, WC Characterized only, not tested in production. 2. E2, E1, E0 input impedance when the memory is selected (after a Start condition). ...
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... Characterized value, not tested in production. 3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle t 4. The new M24C64-W devices (identified by the process letter K) offer I 26/42 M24C64-W M24C64-R M24C64-F M24C64-DF Test conditions (see ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF Table 14. DC characteristics (M24C64-R, device grade 6) Symbol Parameter Input leakage current I LI (SCL, SDA) I Output leakage current LO I Supply current (Read Supply current (Write) CC0 I Standby supply current CC1 Input low voltage V IL (SCL, SDA, WC) ...
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... Only for devices identified with process letter K. 3. Characterized value, not tested in production. 4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle t 28/42 M24C64-W M24C64-R M24C64-F M24C64-DF (1) Test conditions to those in Table ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF Table 16. 400 kHz AC characteristics Symbol Alt SCL t t CHCL HIGH t t CLCH LOW ( QL1QL2 XH1XH2 XL1XL2 DXCH SU:DAT t t CLDX HD:DAT ( CLQX DH ( CLQV CHDL SU:STA t t DLCL HD:STA ...
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... Rbus × Cbus time constant is within the values specified WC=0 set up time condition to enable the execution of a WRITE command. 8. WC=0 hold time condition to enable the execution of a WRITE command. 30/42 M24C64-W M24C64-R M24C64-F M24C64-DF (1) Parameter Clock frequency Clock pulse width high ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF Figure 13. Maximum Figure 14. Maximum value versus bus parasitic capacitance (C bus C bus at maximum frequency f value versus bus parasitic capacitance C bus C bus at maximum frequency f Doc ID 16891 Rev 27 DC and AC parameters ) for bus = 400 kHz C ) for ...
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... DC and AC parameters Figure 15. AC waveforms 32/42 M24C64-W M24C64-R M24C64-F M24C64-DF Doc ID 16891 Rev 27 ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF 9 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline 1 ...
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... SO8N – 8 lead plastic small outline, 150 mils body width, package data Symbol ccc Values in inches are converted from mm and rounded to four decimal digits. 34/42 M24C64-W M24C64-R M24C64-F M24C64-DF A ccc millimeters Typ Min Max 1.750 0.100 0.250 1.250 0.280 0.480 0.170 0.230 ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF Figure 18. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline 1. Drawing is not to scale. Table 20. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data Symbol Values in inches are converted from mm and rounded to four decimal digits. ...
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... (2) eee 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. 36/42 M24C64-W M24C64-R M24C64-F M24C64-DF millimeters Typ Min Max 0.550 0.450 0.600 0.020 0.000 ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF Figure 20. WLCSP-R 5-bump wafer-length chip-scale package outline 1. Drawing is not to scale. 2. The index on the wafer back side (circle) is above the index of the bump side (triangle/arrow). Table 22. WLCSP-R 5-bump wafer-length chip-scale package mechanical data Symbol ( ...
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... F G aaa eee 1. These data are preliminary. 2. Values in inches are converted from mm and rounded to four decimal digits. 3. Dimension measured at the maximum bump diameter parallel to primary datum Z. 38/42 M24C64-W M24C64-R M24C64-F M24C64-DF millimeters Typ Min Max 0.315 0.300 0.330 0.115 0.200 0.160 1 ...
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... M24C64-W M24C64-R M24C64-F M24C64-DF 10 Part numbering Table 24. Ordering information scheme Example: Device type 2 M24 = I C serial access EEPROM Device function C64 = 64 Kbit (8192 x 8) Device family Blank: Without Identification page D: With additional Identification page Operating voltage 5.5 V ...
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... Document revision history Date Revision 14-Mar-2011 07-Apr-2011 18-May-2011 08-Sep-2011 40/42 M24C64-W M24C64-R M24C64-F M24C64-DF Updated information concerning E2, E1, E0 for the WLCSP package: – note under Figure 3: 5-bump WLCSP connections (top view) 22 – comment under Figure 5: Device select code – note 3 under Table 2: Device select code ...
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... Table 22: WLCSP-R 5-bump wafer-length chip- 26 scale package mechanical Datasheet split into: – M24C64-DF, M24C64-W, M24C64-R,M24C64-F (this datasheet) for tandard products (range 6), – M24C64-125 datasheet for automotive products (range 3). Added 8-bump thin WLCSP. Updated single supply voltage and number of Write cycles on cover page ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 42/42 M24C64-W M24C64-R M24C64-F M24C64-DF Please Read Carefully: © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies www ...