M24C64-W STMICROELECTRONICS [STMicroelectronics], M24C64-W Datasheet - Page 20

• Manufacturer Part Number: M24C64-W
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Instructions
5.2
5.2.1
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Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
For the Read instructions, after each byte read (data out), the device waits for an
acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge
during this 9th time, the device terminates the data transfer and switches to its Standby
mode.
Figure 11. Read mode sequences
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
Current
Address
Read
Random
Address
Read
Sequential
Current
Read
Sequention
Random
Read
11) but without sending a Stop condition. Then, the bus master sends another Start
Dev sel *
Dev sel *
ACK
Dev sel
Dev sel
Data out N
R/W
R/W
R/W
Doc ID 16891 Rev 27
ACK
ACK
ACK
ACK
R/W
NO ACK
Data out 1
Byte addr
Byte addr
Data out
NO ACK
ACK
ACK
ACK
M24C64-W M24C64-R M24C64-F M24C64-DF
Byte addr
Byte addr
ACK
ACK
ACK
Data out N
Dev sel *
Dev sel *
NO ACK
R/W
ACK
ACK
R/W
Data out1
Data out
NO ACK
AI01105d
ACK