ATA5771_09 ATMEL [ATMEL Corporation], ATA5771_09 Datasheet - Page 208

• Manufacturer Part Number: ATA5771_09
• Description: Microcontroller with UHF ASK/FSK Transmitter
• Manufacturer: ATMEL [ATMEL Corporation]

18.10.4
7701C–AVR–12/08
ADCSRB – ADC Control and Status Register B
• Bits 7 – BIN: Bipolar Input Mode
The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected
by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided conversions
are supported and the voltage on the positive input must always be larger than the voltage on
the negative input. Otherwise the result is saturated to the voltage reference. In the bipolar mode
two-sided conversions are supported and the result is represented in the two’s complement
form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits +
1 sign bit.
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
See
• Bit 5 – Res: Reserved Bit
This bit is reserved bit in the ATtiny24/44/84 and will always read as what was wrote there.
• Bit 4 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a comple the description of this bit, see
page
• Bit 3 – Res: Reserved Bit
This bit is reserved bit in the ATtiny24/44/84 and will always read as what was wrote there.
• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion
will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-
ger source that is cleared to a trigger source that is set, will generate a positive edge on the
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set
Table 18-7.
Bit
0x03 (0x23)
Read/Write
Initial Value
”ADCSRB – ADC Control and Status Register B” on page
154.
ADTS2
0
0
0
0
1
ADC Auto Trigger Source Selections
R/W
BIN
7
0
ACME
ADTS1
R/W
6
0
0
0
1
1
0
R/W
5
–
0
ADLAR
R/W
ADTS0
4
0
0
1
0
1
0
”ADCL and ADCH – ADC Data Register” on
R/W
3
–
0
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter0 Compare Match A
Timer/Counter0 Overflow
ADTS2
R/W
2
0
136.
ATtiny24/44/84
ADTS1
R/W
1
0
ADTS0
R/W
0
0
.
ADCSRB
155