ATA5771_09 ATMEL [ATMEL Corporation], ATA5771_09 Datasheet - Page 226

• Manufacturer Part Number: ATA5771_09
• Description: Microcontroller with UHF ASK/FSK Transmitter
• Manufacturer: ATMEL [ATMEL Corporation]

21.8
21.8.1
21.8.2
21.8.3
7701C–AVR–12/08
High-voltage Serial Programming Algorithm
Enter High-voltage Serial Programming Mode
Considerations for Efficient Programming
Chip Erase
To program and verify the ATtiny24/44/84 in the High-voltage Serial Programming mode, the fol-
lowing sequence is recommended (See instruction formats in
The following algorithm puts the device in High-voltage Serial Programming mode:
1. Apply 4.5 - 5.5V between V
2. Set RESET pin to “0” and toggle SCI at least six times.
3. Set the Prog_enable pins listed in
4. Apply V
5. Shortly after latching the Prog_enable signature, the device will activly output data on the
6. Wait at least 50 µs before giving any serial instructions on SDI/SII.
Table 21-14. High-voltage Reset Characteristics
The loaded command and address are retained in the device during programming. For efficient
programming, the following should be considered.
• The command needs only be loaded once when writing or reading multiple memory locations.
• Skip writing the data value 0xFF that is the contents of the entire EEPROM (unless the
• Address High byte needs only be loaded before programming or reading a new 256 word
The Chip Erase will erase the Flash and EEPROM
not reset until the Program memory has been completely erased. The Fuse bits are not
changed. A Chip Erase must be performed before the Flash and/or EEPROM are re-
programmed.
Note:
1. Load command “Chip Erase” (see
2. Wait after Instr. 3 until SDO goes high for the “Chip Erase” cycle to finish.
3. Load Command “No Operation”.
Supply Voltage
V
4.5V
5.5V
EESAVE Fuse is programmed) and Flash after a Chip Erase.
window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes
reading.
CC
ns.
after the High-voltage has been applied to ensure the Prog_enable signature has been
latched.
Prog_enable[2]/SDO pin, and the resulting drive contention may increase the power con-
sumption. To minimize this drive contention, release the Prog_enable[2] pin after t
has elapsed.
1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
HVRST
- 5.5V to RESET. Keep the Prog_enable pins unchanged for at least t
RESET Pin High-voltage Threshold
CC
and GND.
V
11.5V
11.5V
HVRST
Table 21-13 on page 172
Table 21-15 on page
(1)
memories plus Lock bits. The Lock bits are
176).
Minimum High-voltage Period for
Table 21-15 on page
to “000” and wait at least 100
Latching Prog_enable
ATtiny24/44/84
100 ns
100 ns
t
HVRST
176):
HVRST
HVRST
173