X4283 INTERSIL [Intersil Corporation], X4283 Datasheet - Page 2

no-image

X4283

Manufacturer Part Number
X4283
Description
CPU Supervisor with 128K EEPROM
Manufacturer
INTERSIL [Intersil Corporation]
Datasheets

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
X4283
Manufacturer:
XICOR
Quantity:
20 000
Part Number:
X4283S8I
Manufacturer:
Intersil
Quantity:
3 950
Company:
Part Number:
X4283V8
Quantity:
1 042
Part Number:
X4283V8-2.7A
Manufacturer:
XICOR
Quantity:
20 000
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as 64 bytes per page.
The device features an 2-wire interface and software
protocol allowing operation on an 2-wire bus.
PIN DESCRIPTION
(SOIC)
Pin
1
2
3
4
5
6
7
8
(TSSOP)
Pin
3
4
5
6
7
8
1
2
RESET/
RESET
Name
SDA
SCL
V
2
V
WP
S
S
CC
SS
0
1
Device Select Input
Device Select Input
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V
tive until V
goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW
longer than the selectable Watchdog time out period. A falling edge on SDA, while
SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes active on power-up
and remains active for 250ms after the power supply stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or
open collector outputs. This pin requires a pull up resistor and the input buffer is al-
ways active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the
control register.
Supply Voltage
CC
X4283, X4285
rises above the minimum V
CC
falls below the minimum V
PIN CONFIGURATION
Function
RST/RST
CC
sense level for 250ms. RESET/RESET
V
V
WP
CC
S
S
S
S
SS
0
1
0
1
8-Pin JEDEC SOIC
8-Pin TSSOP
1
2
3
4
1
2
3
4
CC
sense level. It will remain ac-
8
7
6
5
8
7
6
5
V
WP
SCL
SDA
SCL
SDA
V
RST/RST
CC
SS
March 29, 2005
FN8121.0

Related parts for X4283