X4283 INTERSIL [Intersil Corporation], X4283 Datasheet - Page 6

• Manufacturer Part Number: X4283
• Description: CPU Supervisor with 128K EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

The state of the Control Register can be read at any
time by performing a random read at address FFFFh.
Only one byte is read by each register read operation.
The X4283/85 resets itself after the first byte is read.
The master should supply a stop condition to be con-
sistent with the bus protocol, but a stop is not required
to end this operation.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits
of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a nonvolatile
write cycle, so the device is ready for the next opera-
tion immediately after the stop condition.
BP2, BP1, BP0: Block Protect Bits (Nonvolatile)
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block pro-
tect bits will prevent write operations to one of eight
segments of the array.
WPEN WD1 WD0 BP1 BP0
0
0
0
0
1
1
1
1
7
0
0
1
1
0
0
1
1
0
1
0
1 0000h - 3FFFh
0
1
0
1
6
3000h - 3FFFh
2000h - 3FFFh
Protected Addresses
000h - 1FFh
000h - 07Fh
000h - 0FFh
None (factory setting)
000h - 03Fh
5
(Size)
4
(128 bytes)
(256 bytes)
(512 bytes)
(64 bytes)
(16K bytes)
(4K bytes
(8K bytes
6
3
)
)
RWEL WEL BP2
Upper 1/2 (Q3,Q4)
2
First 2 pgs (P2)
First 4 pgs (P4)
First 8 pgs (P8)
Upper 1/4 (Q4)
First Page (P1)
Full Array (All)
Array Lock
None
1
X4283, X4285
0
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
Write Protect Enable
These devices have an advanced Block Lock scheme
that protects one of eight blocks of the array when
enabled. It provides hardware write protection through
the use of a WP pin and a nonvolatile Write Protect
Enable (WPEN) bit. Four of the 8 protected blocks
match the original Block Lock segments and this pro-
tection scheme is fully compatible with the current
devices using 2 bits of block lock control (assuming
the BP2 bit is set to 0).
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Control Register control the
programmable Hardware Write Protect feature. Hard-
ware Write Protection is enabled when the WP pin and
the WPEN bit are HIGH and disabled when either the
WP pin or the WPEN bit is LOW. When the chip is
Hardware Write Protected, nonvolatile writes as well as
to the block protected sections in the memory array
cannot be written. Only the sections of the memory
array that are not block protected can be written. Note
that since the WPEN bit is write protected, it cannot be
changed back to a LOW state; so write protection is
enabled as long as the WP pin is held HIGH.
WD1
0
0
1
1
WD0
0
1
0
1
Watchdog Time Out Period
disabled (factory setting)
600 milliseconds
200 milliseconds
1.4 seconds
March 29, 2005
FN8121.0