X4283 INTERSIL [Intersil Corporation], X4283 Datasheet - Page 3

• Manufacturer Part Number: X4283
• Description: CPU Supervisor with 128K EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X4283/85 activates a
Power-on Reset Circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.
– It prevents the system microprocessor from starting
– It prevents the processor from operating prior to sta-
– It allows time for an FPGA to download its configura-
– It prevents communication to the EEPROM, greatly
When V
for
RESET/RESET allowing the system to begin opera-
tion.
LOW VOLTAGE MONITORING
During operation, the X4283/85 monitors the V
and asserts RESET/RESET if supply voltage falls
below a preset minimum V
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V
V
Figure 1. Set V
TRIP
SCL
to operate with insufficient voltage.
bilization of the oscillator.
tion prior to initialization of the circuit.
reducing the likelihood of data corruption on power-
up.
SDA
WP
200ms
for 200ms.
CC
exceeds the device V
0 1 2 3 4 5 6 7
TRIP
(nominal)
A0h
Level Sequence (V
3
TRIP
the
CC
. The RESET/RESET
returns and exceeds
TRIP
0 1 2 3 4 5 6 7
circuit
threshold value
CC
V
P
= desired V
= 12-15V
00h
releases
CC
level
X4283, X4285
TRIP
0 1 2 3 4 5 6 7
values WEL bit set)
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to
LOW periodically, while SCL is HIGH (this is a start bit)
prior to the expiration of the watchdog time out period to
prevent a RESET/RESET signal. The state of two non-
volatile control bits in the Status Register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time-Out, any
in-progress communications are terminated. While
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Non-volatile writes in-progress when RESET/RESET
goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
The X4283/85 is shipped with a standard V
old (V
normal operating and storage conditions. However, in
applications where the standard V
right, or if higher precision is needed in the V
value, the X4283/85 threshold may be adjusted. The
procedure is described below, and uses the applica-
tion of a nonvolatile control signal.
CC
01h
THRESHOLD RESET PROCEDURE
TRIP
) voltage. This value will not change over
0 1 2 3 4 5 6 7
00h
TRIP
is not exactly
CC
March 29, 2005
thresh-
FN8121.0
TRIP