ISPPACCLK5316S-01T48C LATTICE [Lattice Semiconductor], ISPPACCLK5316S-01T48C Datasheet - Page 19

• Manufacturer Part Number: ISPPACCLK5316S-01T48C
• Description: In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
When the PLL is selected (PLL_BYPASS=LOW) and locked, the output frequency of each V divider (f
culated as:
where
Note that because the feedback may be taken from any V divider, V
Because the VCO has an operating frequency range spanning 160 MHz to 400 MHz, and the V dividers provide
division ratios from 1 to 32, the ispClock5300S can generate output signals ranging from 2.5 MHz to 267 MHz.
PLL_BYPASS Mode
The PLL_BYPASS mode is provided so that input reference signals can be coupled through to the outputs without
using the PLL functions. When PLL_BYPASS mode is enabled (PLL_BYPASS=HIGH), the reference clock is
routed directly to the inputs of the V dividers. The output frequency for a given V divider (f
When PLL_BYPASS mode is enabled, features such as lock detect and skew generation are unavailable and the
output clock is inverted when V
Internal/External Feedback Support
The PLL feedback path can be sourced internally or externally through an output pin. When the internal feedback
path is selected, one can use all output pins for clock distribution. The programmable skew feature for the feedback
path is available in both feedback modes.
Reference and External Feedback Inputs
The ispClock5300S provides configurable, internally-terminated inputs for both clock reference and feedback sig-
nals.
The reference clock inputs pins can be interfaced with either one differential input (REFP, REFN) or two single-
ended (REFA, REFB) inputs with the active clock selection control through REFSEL pin. The following diagram
shows the possible reference clock configurations. Note: When the reference clock inputs are configured as differ-
ential input, the REFSEL pin should be grounded.
Table 2. REFSEL Operation for ispClock5300S Programmed as Single-Ended Clock Inputs
Supported input logic reference standards:
f
f
V
V
• LVTTL (3.3V)
• LVCMOS (1.8V, 2.5V, 3.3V)
• SSTL2
• SSTL3
• HSTL
k
ref
fbk
k
is the frequency of V divider k
is the output divider K
is the input reference frequency
is the setting of the V divider used to close the PLL feedback path
K
=1.
REFSEL
0
1
f
k
=
f
k
=
f
ref
19
f
REF
V
V
K
V
Selected
fbk
k
REFB
REFA
Input
k
and V
ispClock5300S Family Data Sheet
fbk
may refer to the same divider.
K
) will be determined by
k
) may be cal-
(1)
(2)