ISPPACCLK5316S-01T48C LATTICE [Lattice Semiconductor], ISPPACCLK5316S-01T48C Datasheet - Page 36

• Manufacturer Part Number: ISPPACCLK5316S-01T48C
• Description: In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
ispClock5300S Family Data Sheet
Evaluation Fixture
Included in the basic ispClock5300S Design Kit is an engineering prototype board that can be connected to the
®
parallel port of a PC using a Lattice ispDOWNLOAD
cable. It demonstrates proper layout techniques for the
ispClock5300S and can be used in real time to check circuit operation as part of the design process. Input and out-
put connections (SMA connectors for all RF signals) are provided to aid in the evaluation of the ispClock5300S for
a given application. (Figure 31).
Part Number
Description
PAC-SYSTEMCLK5312S
Complete system kit, evaluation board, ispDOWNLOAD cable and software.
Figure 31. Download from a PC
PAC-Designer
Software
Other
System
Circuitry
ispDownload
Cable (6')
4
ispClock5300S
Device
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the ispClock5300S is facilitated via an IEEE 1149.1 test
access port (TAP). It is used by the ispClock5300S both as a serial programming interface, and for boundary scan
test purposes. A brief description of the ispClock5300S JTAG interface follows. For complete details of the refer-
ence specification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std.
1149.1-1990 (which now includes IEEE Std. 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the
ispClock5300S. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct
sequence, instructions are shifted into an instruction register which then determines subsequent data input, data
output, and related operations. Device programming is performed by addressing the configuration register, shifting
data in, and then executing a program configuration instruction, after which the data is transferred to internal
2
E
CMOS cells. It is these non-volatile cells that store the configuration of the ispClock5300S. A set of instructions
are defined that access all data registers and perform other internal control operations. For compatibility between
compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are functionally spec-
ified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by the manu-
facturer. The two required registers are the bypass and boundary-scan registers. Figure 32 shows how the
instruction and various data registers are organized in an ispClock5300S.
36