ISPPACCLK5316S-01T48C LATTICE [Lattice Semiconductor], ISPPACCLK5316S-01T48C Datasheet - Page 9

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ISPPACCLK5316S-01T48C

Manufacturer Part Number
ISPPACCLK5316S-01T48C
Description
In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
Lattice Semiconductor
Output Rise and Fall Times – Typical Values
Output Test Loads
Figures 6 and 7 show the equivalent termination loads used to measure rise/fall times, output timing adders and
other selected parameters as noted in the various tables of this data sheet.
Figure 6. CMOS Termination Load
Figure 7. eHSTL/HSTL/SSTL Termination Load
LVTTL
LVCMOS 1.8V
LVCMOS 2.5V
LVCMOS 3.3V
SSTL18
SSTL2
SSTL3
HSTL
eHSTL
1. See Figures 6 and 7 for test conditions.
2. Measured between 20% and 80% points.
Output Type
ispCLOCK
Slew 1 (Fastest)
0.54
0.75
0.57
0.55
0.55
0.50
0.50
0.60
0.55
Zo = HSTL: ~20Ω
t
R
ispClock
SSTL: 40Ω
0.76
0.69
0.69
0.77
0.40
0.40
0.45
0.45
0.40
Zo = 50Ω
t
F
50Ω/3"
0.60
0.88
0.65
0.60
t
R
Slew 2
50Ω/3"
50Ω/36"
0.87
0.78
0.78
0.87
t
F
9
50Ω/36"
0.78
0.83
0.99
0.78
t
R
1, 2
50Ω
Slew 3
ispClock5300S Family Data Sheet
1.26
1.11
0.98
1.26
950Ω
t
F
SCOPE
50Ω 5pF
Slew 4 (Slowest)
1.05
1.20
1.65
1.05
950Ω
VTERM
t
R
SCOPE
50Ω 5pF
1.88
1.68
1.51
1.88
t
F
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns

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