ISPPACCLK5316S-01T48C LATTICE [Lattice Semiconductor], ISPPACCLK5316S-01T48C Datasheet - Page 2

• Manufacturer Part Number: ISPPACCLK5316S-01T48C
• Description: In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
General Description
The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution
applications. The ispClock5312S, the first member of the ispClock5300S family, provides up to 12 single-ended
ultra low skew outputs. Each pair of outputs may be independently configured to support separate I/O standards
(LVTTL, LVCMOS -3.3V, 2.5V, 1.8, SSTL, HSTL) and output frequency. In addition, each output provides indepen-
dent programmable control of termination, slew-rate, and timing skew. All configuration information is stored on-
chip in non-volatile E
The ispClock5300S devices provide extremely low propagation delay (zero-delay) from input to output using the
on-chip low jitter high-performance PLL. A set of three programmable 5-bit counters can be used to generate three
frequencies derived from the PLL clock. These counters are programmable in powers of 2 only (1, 2, 4, 8, 16, 32).
The clock output from any of the V-dividers can then be routed to any clock output pin through the output routing
matrix. The output routing matrix, in addition, also enables routing of reference clock inputs directly to any output.
The ispClock5300S device can be configured to operate in four modes: zero delay buffer mode, dual non-zero
delay buffer mode, non-zero delay buffer mode with output dividers, and combined zero-delay and non-zero delay
buffer mode.
The core functions of all members of the ispClock5300S family are identical. Table 1 summarizes the
ispClock5300S device family.
Table 1. ispClock5300S Family
Figure 1. ispClock5304S Functional Block Diagram
REFA_REFP
REFB_REFN
VTT_REFA
VTT_REFB
VTT_FBK
REFSEL
FBK
ispClock5320S
ispClock5316S
ispClock5312S
ispClock5308S
ispClock5304S
2
Device
CMOS
+
0
1
®
memory.
DETECT
DETECT
L
LOCK
PHASE
O
TDI
C
K
JTAG INTERFACE
TMS
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
Number of Programmable
RESET
TCK
FILTER
LOOP
TDO
Clock Inputs
VCO
2
P
L
L
_
B
1
0
Y
P
A
S
S
OUTPUT ENABLE
OEX
DIVIDERS
CONTROLS
OUTPUT
5-bit
5-bit
5-bit
V0
V1
V2
ispClock5300S Family Data Sheet
OEY
OUTPUT ROUTING
Number of Programmable
Single-Ended Outputs
MATRIX
CONTROL
CONTROL
SKEW
SKEW
20
16
12
8
4
DRIVERS
DRIVERS
OUTPUT
OUTPUT
BANK_0A
BANK_0B
BANK_1A
BANK_1B