TMP47C101 Toshiba Semiconductor, TMP47C101 Datasheet
TMP47C101
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TMP47C101 Summary of contents
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... TOSHIBA TLCS-47E Series CMOS 4-bit Microcontroller TMP47C101P, TMP47C201P, TMP47C101M, TMP47C201M Part No. ROM TMP47C101P 1024 x 8-bit TMP47C101M TMP47C201P 2048 x 8-bit TMP47C201M Features • 4-bit single chip microcomputer • Instruction execution time: 1.3 s (at 6MHz) • Low voltage operation: 2.2V (at 2MHz RC) • 89 basic instructions - Instruction set is the same as TLCS-47 series • ...
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... TMP47C101/201 Pin Assignment (Top View) Pin Function Pin Name Input/Output R43 to R40 I/O R53 to R50 R81 (T2) I/O (Input) R80 (INT2) XIN Input XOUT Output RESET Input HOLD (INT1) I/O (Input) VDD Power Supply VSS 2/32 4-bit I/O port with latch. When used as input port, the latch must be set to “1”. ...
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... H Register, L Register • 2.4 Data Memory (RAM) - Stack - Stack Pointer Word (SPW) - Data Counter (DC) TOSHIBA CORPORATION • 2.5 ALU, Accumulator • 2.6 Flags • 2.7 System Controller • 2.8 Interrupt Controller • 2.9 Reset Circuit Peripheral Hardware Function • 3.1 I/O Ports • 3.2 Interval Timer • 3.3 Timer/Counters (TC1, TC2) TMP47C101/201 3/32 ...
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... TMP47C101/201 2. Internal CPU Function 2.1 Program Counter (PC) The program counter is a 11-bit binary counter which indicates the address of the program memory storing the next instruc- tion to be executed.Normally, the PC is incremented by the The PC can directly address a 2048-byte address space. However, with the short branch, the following points must be considered: • ...
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... TMP47C101/201 with the DC value being 7AO being 58 H “8” is stored in the accumulator; when [LDH A, @DC+] instruction is executed, “ ...
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... TMP47C101/201 2.3 H Register and L Register The H register and L register are 4-bit general registers. They are also used as a register pair (HL) for the data memory (RAM) addressing pointer. The RAM consists of pages, each page being 16 words long (1 word = 4 bits). The H register specifies a page and the L register specifi ...
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... In this mode, an address in zero-page (addresses 00 through 0F ond byte (operand) in the instruction field. Example: ST #3, 05H ; Figure 2-5. Addressing Mode Data Counter (DC) Count registers of the timer/counters (TC1, TC2) Zero-page Figure 2-6. Data Memory Map (47C201) TMP47C101/201 ; Acc RAM [ specified by the lower 4 bits of the sec- H RAM [ ...
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... TMP47C101/201 (1) Stack The stack provides the area in which the return address is saved before a jump is performed to the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When a subroutine call instruction is executed, the contents (the return address) of the program counter are saved; ...
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... When none of timer/counter 1 and timer/counter 2 are used, the stack is usable from location 14. When both timer/counter 1 and timer/counter 2 are used, the data memory locations at addresses 77 and 7B (37 and 3B for the 47C101) can be used store the user-processed data. TMP47C101/201 H 9/32 ...
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... TMP47C101/201 (5) Zero-page The 16 words (at addresses 00 zero page of the data memory can be used as the user flags or pointers by using zero-page addressing mode instructions (comparison, addition, transfer, and bit manipulation), providing enhanced efficiency in pro- gramming. Figure 2-10. Data Memory Capacity and Address Assignment When power-on is performed, the contents of the RAM become unpredictable, so that they must be initialized by the initialization routine ...
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... When a branch instruction is executed upon set or clear of the SF according to the condition specifi instruction, this instruction becomes a conditional branch instruction. During reset, the SF is initialized to “1”, other flags are not affected. TMP47C101/201 ) to the ALU to hold the in 11/32 ...
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... TMP47C101/201 (4) General flag (GF) This is a 1-bit general-purpose flag which can be set, cleared, or tested by program. 2.7. System Controller Figure 2-14. Clock Generator and Timing Generator 2.7.1 Clock Generator The clock generator provides the basic clock pulse (CP) by which the system clock to be supplied to the CPU and the peripheral hardware is produced ...
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... The instruction set of the TLCS-47 series consists of 1-cycle instructions and 2-cycle instructions. The former requires 1 cycle for their execution; the latter, 2 cycles. Each instruction cycle consists of 4 states (S1 through S4). Each state consists of 2 basic clock pulses. Figure 2-17. Instruction Cycle TMP47C101/201 22 [Hz]. During reset, the 13/32 ...
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... TMP47C101/201 2.7.4 Hold Operating Mode The hold feature stops the system and holds the system’s internal states active before stop with a low power. The hold operation is controlled by the command register (OP10) and the HOLD pin input. The HOLD pin input state can be known by the status register (IPOE) ...
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... Example: To start the hold operation in the edge-sen- Figure 2-20. Edge-Sensitive Release Mode (2) Releases Hold Operating Mode The hold operating mode is released in the following sequence however, when the DD SS TMP47C101/201 sitive release mode (the warm-up time = 14 2 /fc #0101B ; OP10 0101 OUT A, %OP10 The oscillator starts Warm-up is performed to acquire the time for stabi- lizing oscillation ...
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... TMP47C101/201 The warm-up time is obtained by dividing the basic clock by the interval timer, so that, if the frequency at releasing the hold operation is unstable, the warm-up time shown in Figure 2-18. includes an error. There- fore, the warm-up time must be handled as an approx- imate value. The hold operation is also released by setting the RESET pin to the low level ...
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... IL, r], [DICLR IL, r], and [CLR IL, r]) to make them cancel interrupt requests or initialize by program. When the value of instruction field (r) is “0”, the interrupt latch is cleared; when the value is “1”, the IL is held. Note that the ILs cannot be set by instruction. TMP47C101/201 ) is shared by 1 17/32 ...
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... TMP47C101/201 Example 1: To enable IOVF1, INT1, and INT2 interrupts. LD A,#0101B XCH A,EIR EICLR IL,111111B Example 2: To set the EIF to “1”, and to clear the inter- rupt latches except ITMR to “0”. EICLR IL,000010B 2.8.2 Interrupt Processing An interrupt request is held until the interrupt is accepted or the IL is cleared by the reset of the interrupt latch operation instruction ...
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... When the RESET pin input goes high, the reset is cleared and program execution starts from address 000 pin is a hysteresis input with a pull-up resistor (220k typ.). Ex- ternally attaching a capacitor and a diode implement a simpli- fied power-on-reset operation Figure 2-23. Simplified Power-On-Reset TMP47C101/201 . The RESET H 19/32 ...
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... TMP47C101/201 3. Peripheral Hardware Function 3.1 Ports The data transfer with the external circuit and the command/ status/data transfer with the internal circuit are performed by using the I/O instructions (13 kinds). There are 4 types of ports: I/O port ; Data transfer with external cir- cuit Command register ; Control of internal circuit Status register ...
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... Table 3-1. Port Address Assignments and Available I/O Instructions TOSHIBA CORPORATION TMP47C101/201 21/32 ...
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... TMP47C101/201 (1) Ports R4 (R43 to R40), R5 (R53 to 50) These ports are 4-bit I/O ports with a latch. When used as an input port, the latch must be set to “1”. The latch is initialized to “1” during reset. Port R4 can directly drive LEDs. These 2 ports (8 pins) can be set, cleared, and tested for each bit as specifi ...
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... The interval timer is not cleared by command, so that the first interrupt TOSHIBA CORPORATION Figure 3-4. Port R8 and HOLD (INT1) Pin may occur earlier than the preset interrupt period. Example: To set the interval timer interrupt frequency to LD OUT Figure 3-5. Command Register TMP47C101/201 12 fc/2 [Hz]. A, #0110B A, %OP19 23/32 ...
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... TMP47C101/201 3.3 Timer/Counters (TC1,TC2) The 47C101/201 contain two 12-bit timer/counters (TC1, TC2). RAM addresses are assigned to the count register in unit of 4 bits, permitting the initial value setting and counter reading Figure 3-16. Count Registers of the Timer/Counters (TC1, TC2) 3.3.1 Functions of Timer/Counters The timer/counters provide the following functions: ...
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... Figure 3-9. Event Counter Timing Chart interval. When an internal pulse rate of fc/2 operation is inserted once every 128 instruction cycles, so that the apparent instruction execution speed drops by (1/127) x 100 = 0.8%. For example, the instruction execution speed drops to 2.016 s. TMP47C101/201 to 000 #0100B ; OP1D 01** OUT ...
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... TMP47C101/201 Example: To generate an overflow interrupt ( 4MHz) by the TC1 after 100ms. LD HL, #0F4H ST #9, @HL+ ST #7, @HL+ ST #0EH, @HL #1000B OUT A, %OP1C LD A, #0100B A EIR EICLR IL, 110111B ; Internal Pulse Rate 10 fc/2 [Hz] 14 fc/2 18 fc/2 22 fc/2 (3) Pulse width measurement mode In the pulse width measurement mode, the timer/ counter increments with the pulse obtained by sam- pling the external pins (T2) by the internal pulse ...
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... Input/Output Circuitry (1) Control pins (2) I/O Ports TOSHIBA CORPORATION The input/output circuitries of the 47C101/201 control pins are shown below, any one of the circuitries can be chosen by a code (FA mask option. TMP47C101/201 27/32 ...
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... TMP47C101/201 Electrical Characteristics Absolute Maximum Ratings (V SS Parameter Supply Voltage Input Voltage Output Voltage Output Current (Per 1 pin) Output Current (Total) Power Dissipation [ opr Soldering Temperature (time) Storage Temperature Operating Temperature Recommended Operating Conditions (V Parameter Symbol Supply Voltage Except Hysteresis Input ...
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... A 2.4 – 2.0 – 1.6mA – – – – 1.0V – – 2 – 1 – 0.5 – 0.5 Min. Typ. 1.3 – 1.9 3.2 80 160 – 80 160 TMP47C101/201 Max. Unit – 450 – V – 0.4 V 0.1 – – Max. Unit 20 s – ns 29/32 ...
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... TMP47C101/201 Recommended Oscillating Conditions (V (1) 6MHz Ceramic Resonator CSA6.00MGU (MURATA) KBR-6.00MS (KYOCERA) EFOEC6004A4 (NATIONAL) (2) 4MHz Ceramic Resonator CSA4.00MG (MURATA) KBR-4.00MS (KYOCERA) EFOEC4004A4 (NATIONAL) Crystal Oscillator 204B-6F 4.0000 (TOYOCOM) C (3) 400kHz Ceramic Resonator CSB400B (MURATA) KBR-400B (KYOCERA) EFOA400K04B (NATIONAL) C (4) ...
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... Typical Characteristics TOSHIBA CORPORATION TMP47C101/201 31/32 ...
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... TMP47C101/201 32/32 Notes TOSHIBA CORPORATION ...