TMP47C101 Toshiba Semiconductor, TMP47C101 Datasheet - Page 19

• Manufacturer Part Number: TMP47C101
• Description: (TMP47C101 / TMP47C201) CMOS 4-bit Microcontroller
• Manufacturer: Toshiba Semiconductor

TOSHIBA CORPORATION
flags are automatically saved or restored but the accumulator
and other registers are not. If it is necessary to save or restore
them, it must be performed by program as shown in the fol-
lowing example. To perform the multi-interrupt, the saving
RAM area never be overlapped.
2.8.3 External Interrupt
When an external interrupt (INT1 or INT2) occurs, the interrupt
latch is set at the falling edge of the corresponding pin input
(INT1 or INT2). The external interrupt input is the hysteresis
type, each of high and low level time requires 2 or more
instruction cycles for a correct interrupt operation.
In the interrupt processing, the program counter and
Example: To save and restore the accumulator and HL
Note. The lower 2 bits of GSAV1 should be “0’s”.
XCH
XCH
register pair.
HL, GSAV1;
A, GSAV1+2;
Table 2-3. Initialization of Internal States by Reset Operation
RAM GSAV1
RAM GSAV1+2
Figure 2-23. Simplified Power-On-Reset
HL
Acc
it is always accepted in the interrupt enable state (EIF=”1”).
Therefore, INT1 is used for an interrupt with high priority such
as an emergency interrupt. When HOLD (INT1) pin is used for
the I/O port, the INT1 interrupt occurs at the falling edge of the
pin input, so that the interrupt return [RET1] instruction must
be stored at the interrupt entry address to perform dummy in-
terrupt processing.
2.9 Reset Function
When the RESET pin is held to the low level for three or more
instruction cycles when the power voltage is within the operat-
ing voltage range and the oscillation is stable, reset is per-
formed to initialize the internal states.
and program execution starts from address 000
pin is a hysteresis input with a pull-up resistor (220k typ.). Ex-
ternally attaching a capacitor and a diode implement a simpli-
fied power-on-reset operation
The INT1 interrupt cannot be disabled by the EIR, so that
When the RESET pin input goes high, the reset is cleared
TMP47C101/201
H
. The RESET
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