TMP47C101 Toshiba Semiconductor, TMP47C101 Datasheet - Page 16

• Manufacturer Part Number: TMP47C101
• Description: (TMP47C101 / TMP47C201) CMOS 4-bit Microcontroller
• Manufacturer: Toshiba Semiconductor

TMP47C101/201
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Note:
The warm-up time is obtained by dividing the basic
clock by the interval timer, so that, if the frequency at
releasing the hold operation is unstable, the warm-up
time shown in Figure 2-18. includes an error. There-
fore, the warm-up time must be handled as an approx-
imate value. The hold operation is also released by
setting the RESET pin to the low level. In this case, the
normal reset operation follows immediately.
In this case, if a time-constant circuit or the like is
externally attached, the voltage rise of the RESET pin
input occurs after the power voltage rise. If the voltage
To release the hold operation at a low hold voltage, the following
When the power voltage rises from the hold voltage to the operat-
points must be considered:
ing voltage, the RESET pin input is also at the high level and its
voltage rises with the power voltage.
Table 2-2. Interrupt Sources
2.8 Interrupt Function
2.8.1 Interrupt Controller
There are 5 interrupt sources (2 external and 3 internal). The
prioritized multiple interrupt capability is supported. The inter-
rupt latches (IL
vided for the interrupt sources. Each interrupt latch is set to “1”
when an interrupt request is made, asking the CPU to accept
the interrupt. The acceptance of interrupt can be permitted or
prohibited by program through the interrupt enable master flip-
flop (EIF) and interrupt enable register (EIR). When two or more
interrupts occur simultaneously, the one with the highest prior-
ity determined by hardware is serviced first.
level of the RESET pin input gets under the non-
inverted high input voltage of the RESET pin input (the
hysteresis input), a reset operation may happen.
5
through IL
0
) to hold interrupt requests are pro-
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