TMP47C101 Toshiba Semiconductor, TMP47C101 Datasheet - Page 7

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TMP47C101

Manufacturer Part Number
TMP47C101
Description
(TMP47C101 / TMP47C201) CMOS 4-bit Microcontroller
Manufacturer
Toshiba Semiconductor
Datasheet

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2.4 Data Memory (RAM)
The 47C101 has 64 x 4 bits (addresses 00
the data memory (RAM), and the 47C201 has 128 x 4 bits
(addresses 00
ing modes):
(1)
2.4.1 Data Memory Map
Figure 2-6 shows the data memory map. The data memory is
also used for the following special purpose.
The RAM is addressed in one of the three ways (address-
Register-indirect addressing mode
In this mode, a page is specified by the H register and
an address in the page by the L register.
Example: LD A, @HL
Stack and Stack Pointer Word (SPW)
H
through 7F
H
).
;
Acc RAM [HL]
Figure 2-6. Data Memory Map (47C201)
H
through 3F
Figure 2-5. Addressing Mode
H)
of
(2)
(3)
Direct addressing mode
In this mode, an address is directly specified by the 8
bits of the second byte (operand) in the instruction
field.
Example: LD A, 2CH
Zero-page addressing mode
In this mode, an address in zero-page (addresses 00
through 0F
ond byte (operand) in the instruction field.
Example: ST #3, 05H ;
Data Counter (DC)
Count registers of the timer/counters (TC1, TC2)
Zero-page
H
) is specified by the lower 4 bits of the sec-
;
Acc RAM [2C
RAM [05
TMP47C101/201
H
] 3
H
]
7/32
H

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