ispPAC-CLK55xx Lattice Semiconductor, ispPAC-CLK55xx Datasheet - Page 21

• Manufacturer Part Number: ispPAC-CLK55xx
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: Lattice Semiconductor

Lattice Semiconductor
Please note that while the above discussions specify using 50Ω termination impedances, the actual impedance
required to properly terminate the transmission line and maintain good signal integrity may vary from this ideal. The
actual impedance required will be a function of the driver used to generate the signal and the transmission medium
used (PCB traces, connectors and cabling). The ispClock5500’s ability to adjust input impedance over a range of
40Ω to 70Ω allows the user to adapt his circuit to non-ideal behaviors from the rest of the system without having to
swap out components.
Output Drivers
The ispClock5500 provide banks of configurable, internally-terminated high-speed dual-output line drivers. The
ispClock5510 provides five driver banks, while the ispClock5520 provides ten. Each of these driver banks may be
configured to provide either a single differential output signal, or a pair of single-ended output signals. Programma-
ble internal source-series termination allows the ispClock5500 to be matched to transmission lines with imped-
ances ranging from 40 to 70 Ohms. The outputs may be independently enabled or disabled, either from E
configuration or by external control lines. Additionally, each can be independently programmed to provide a fixed
amount of signal delay or skew, allowing the user to compensate for the effects of unequal PCB trace lengths or
loading effects. Figure 18 shows a block diagram of a typical ispClock5500 output driver bank and associated skew
control.
Because of the high edge rates which can be generated by the ispClock5500’s clock output drivers, the VCCO
power supply pin for each output bank should be individually bypassed. Low ESR capacitors with values ranging
from 0.01 to 0.1 µF may be used for this purpose. Each bypass capacitor should be placed as close to its respec-
tive output bank power pins (VCCO and GNDO) pins as is possible to minimize interconnect length and associated
parasitic inductances.
In the case where an output bank is unused, the associated VCCO pin may be either left floating or tied to ground
to reduce quiescent power consumption. We recommend, however, that all unused VCCO pins be tied to ground
where possible. All GNDD pins must be tied to ground, regardless of whether or not the associated bank is used.
Figure 18. ispClock5500 Output Driver and Skew Control
From V-Dividers
Adjust
Adjust
Skew
Skew
Control
Control
Control
21
OE
OE
OE
‘B’ output Driver
Single-ended
‘A’ output Driver
Single-ended
(PECL/LVDS)
Differential
Driver
ispClock5500 Family Data Sheet
BANKxA
BANKxB
2
CMOS