ispPAC-CLK55xx Lattice Semiconductor, ispPAC-CLK55xx Datasheet - Page 26

• Manufacturer Part Number: ispPAC-CLK55xx
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: Lattice Semiconductor

Lattice Semiconductor
Table 6. SGATE Function
Skew Control Units
Each of the ispClock5500’s clock outputs is supported by a skew control unit which allows the user to insert an indi-
vidually programmable delay into each output signal. This feature is useful when it is necessary to de-skew clock
signals to compensate for physical length variations among different PCB clock paths.
Unlike the skew adjustment features provided in many competing products, the ispClock5500’s skew adjustment
feature provides exact and repeatable delays which exhibit extremely low channel-to-channel and device-to-device
variation. This is achieved by deriving all skew timing from the VCO, which results in the skew increment being a lin-
ear function of the VCO period. For this reason, skews are defined in terms of ‘time units’ (TUs), which may be pro-
grammed by the user over a range of 0 to 15. The ispClock5500 family also supports both ‘fine’ and ‘coarse’ skew
modes. In fine skew mode, the unit skew ranges from 195ps to 390 ps, while in the coarse skew mode unit skew
varies from 390ps to 780ps. The value of one TU may be calculated from the VCO frequency (f
lowing expressions:
When an output driver is programmed to support a differential output mode, a single skew setting is applied to both
the BANKxA+ and BANKxB- signals. When the output driver is configured to support a single-ended output stan-
dard, each of the two single-ended outputs may be assigned independent skews.
By using the internal feedback path, and programming a skew into the feedback skew control, it is possible to
implement negative timing skews, in which the clock edge of interest appears at the ispClock5500’s output before
the corresponding edge is presented at the reference input. When the feedback skew unit is used in this way, the
resulting negative skew is added to whatever skew is specified for each output. For example, if the feedback skew
is set to 6TU, BANK1’s skew is 8TU and BANK2’s skew is 3TU, then BANK1’s effective output skew will be 2TU
(8TU-6TU), while BANK2’s effective skew will be -3TU (3TU-6TU). This negative skew will manifest itself as
BANK2’s outputs appearing to lead the input reference clock, appearing as a negative propagation delay.
Please note that the skew control units are only usable when the PLL is selected. In PLL bypass mode
(PLL_BYPASS=1), output skew settings will be ineffective and all outputs will exhibit skew consistent with the
device’s propagation delay and the individual delays inherent in the output drivers consistent with the logic stan-
dard selected.
Coarse Skew Mode
The ispClock5500 family provides the user with the option of obtaining longer skew delays at the cost of reduced
time resolution through the use of coarse skew mode. Coarse skew mode provides TU values ranging from 390ps
(f
coarse skew mode is selected, an additional divide-by-2 stage is effectively inserted between the VCO and the V-
divider bank, as shown in Figure 23. When assigning divider settings in coarse skew mode, one must account for
this additional divide-by-two so that the VCO still operates within its specified range (320-640MHz).
VCO
= 640MHz) to 780ps (f
SGATE Bank Controlled by SGATE?
X
X
0
0
1
1
For fine skew mode,
VCO
= 320MHz), which is twice as long as those provided in fine skew mode. When
YES
YES
YES
YES
NO
NO
TU
=
8f
1
vco
26
Output Polarity
For coarse skew mode,
Inverted
Inverted
Inverted
True
True
True
ispClock5500 Family Data Sheet
TU
Inverted Clock
Inverted Clock
=
Output
Clock
HIGH
Clock
LOW
4f
1
vco
vco
) by using the fol-
(5)