GS8320Z18T ETC, GS8320Z18T Datasheet
GS8320Z18T
Related parts for GS8320Z18T
GS8320Z18T Summary of contents
Page 1
... Synchronous NBT SRAM Functional Description The GS8320Z18/36T is a 36Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles ...
Page 2
... GS8320Z18T Pinout 100 DDQ DDQ DDQ ...
Page 3
GS8320Z36T Pinout 100 DDQ ...
Page 4
TQFP Pin Descriptions Pin Location Symbol 37 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,47, 48, 49, 50, 83, 84, A – ...
Page 5
... GS8320Z18/36 NBT SRAM Functional Block Diagram Rev: 1.01 10/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320Z18/36T-250/225/200/166/150/133 Amps Sense Drivers Write 5/25 Product Preview © 2001, Giga Semiconductor, Inc. ...
Page 6
... A B cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock ...
Page 7
... Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. ...
Page 8
Pipeline and Flow Through Read Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition ...
Page 9
Pipeline Mode Data I/O State Diagram Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.01 10/2001 Specifications cited ...
Page 10
Flow Through Mode Data I/O State Diagram B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.01 10/2001 Specifications cited are subject to ...
Page 11
... SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode ...
Page 12
... GSI NBT SRAMs are fully compatible with these sockets. Pin 66 Connect (NC) on GSI’s GS8320Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS8321Z18/36 NBT SRAM, is often marked as a power pin on other vendor’s NBT compatible SRAMs. Specifically marked V on pipelined parts and V on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ ...
Page 13
Absolute Maximum Ratings ) (All voltages reference Symbol V Voltage Voltage in V DDQ V Voltage on Clock Input Pin CK V Voltage on I/O Pins I/O V Voltage on Other Input Pins ...
Page 14
Power Supply Voltage Ranges Parameter 3.3 V Supply Voltage 2.5 V Supply Voltage 3 I/O Supply Voltage DDQ 2 I/O Supply Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the character ...
Page 15
... Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP) Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper- ature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 1 ...
Page 16
AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
Page 17
Rev: 1.01 10/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320Z18/36T-250/225/200/166/150/133 17/25 Product Preview © 2001, Giga Semiconductor, Inc. ...
Page 18
AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid tKQX Clock to Output in Low-Z Clock Cycle Time Clock to Output Valid Flow Through Clock to Output Invalid tKQX Clock to Output ...
Page 19
Pipeline Mode Read/Write Cycle Timing CKE ADV – – Write Write COMMAND D(A2) D(A1) ...
Page 20
Pipeline Mode No-Op, Stall and Deselect Timing CKE ADV – Write D(A1) COMMAND *Note High (False ...
Page 21
Flow Through Mode Read/Write Cycle Timing CKE ADV – D(A1 Write COMMAND D(A1) *Note High ...
Page 22
Flow Through Mode No-Op, Stall and Deselect Timing CKE ADV –An DQ Write COMMAND D(A1) *Note High (False ...
Page 23
TQFP Package Drawing Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body 13.9 e ...
Page 24
... GS8320Z18T-150 GS8320Z18T-133 GS8320Z36T-250 GS8320Z36T-225 GS8320Z36T-200 GS8320Z36T-166 GS8320Z36T-150 GS8320Z36T-133 GS8320Z18T-250I GS8320Z18T-225I GS8320Z18T-200I GS8320Z18T-166I GS8320Z18T-150I GS8320Z18T-133I GS8320Z36T-250I GS8320Z36T-225I GS8320Z36T-200I GS8320Z36T-166I GS8320Z36T-150I GS8320Z36T-133I Notes: 1. ...
Page 25
... Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 8320Z18_r1 8320Z18_r1; 8320Z18_r1_01 Rev: 1.01 10/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320Z18/36T-250/225/200/166/150/133 Page;Revisions;Reason • Creation of new datasheet • Corrected pinouts—moved A19 from pin 39 to pin 43; changed pin 39 ...