GS8320Z18T ETC, GS8320Z18T Datasheet - Page 4

• Manufacturer Part Number: GS8320Z18T
• Description: (GS8320Z18T/36T) 36Mb Pipelined and Flow Through Synchronous NBT SRAM
• Manufacturer: ETC

100-Pin TQFP Pin Descriptions
Rev: 1.01 10/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
44, 45, 46,47, 48, 49, 50, 83, 84,
63, 62, 59, 58, 57, 56, 53, 52, 51 DQ
18, 19, 22, 23, 24, 25, 28, 29, 30 DQ
58, 59, 62,63, 68, 69, 72, 73, 74 DQ
5,10, 17, 21, 26, 40, 55, 60, 67,
35, 34, 33, 32, 100, 99, 82, 81,
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57, 75, 78, 79,
4, 11, 20, 27, 54, 61, 70, 77
1, 2, 3, 6, 7, 25, 28, 29, 30
13, 12, 9, 8, 7, 6, 3, 2, 1
68, 69, 72, 73, 74, 75,
15, 16, 41, 65, 91
Pin Location
38, 39, 42, 66
78, 79, 80
71, 76, 90
37, 36
43
80
89
93
94
95
96
88
98
97
92
86
85
87
64
14
31
DQ
DQ
DQ
Symbol
A
A
C1
D1
A1
B1
A1
B1
V
ADV
CKE
LBO
2
V
V
A
NC
NC
0
CK
ZZ
FT
–A
B
B
B
B
E
E
E
DDQ
W
G
–DQ
–DQ
–DQ
–DQ
–DQ
–DQ
, A
DD
SS
20
A
B
C
D
1
2
3
19
1
A9
B9
A9
B9
C9
D9
Type
I/O
I/O
I/O
I/O
I/O
I/O
—
—
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
4/25
Byte Write signal for data inputs DQ
Byte Write signal for data inputs DQ
Chip Enable; Active High. For self decoded depth expansion
Chip Enable; Active Low. For self decoded depth expansion
Byte Write signal for data inputs DQ
Byte Write signal for data inputs DQ
Byte A Data Input and Output pins (x18 Version Only)
Byte B Data Input and Output pins (x18 Version Only)
Byte A Data Input and Output pins (x36 Version Only)
Byte B Data Input and Output pins (x36 Version Only)
Byte C Data Input and Output pins (x36 Version Only)
Byte D Data Input and Output pins (x36 Version Only)
Advance/Load; Burst address counter control pin
Pipeline/Flow Through Mode Control; active low
Burst Address Inputs; Preload the burst counter
Clock Input Buffer Enable; active low
GS8320Z18/36T-250/225/200/166/150/133
Address Input (x18 Version Only)
Power down control; active high
No Connect (x18 Version Only)
Linear Burst Order; active low
Output driver power supply
Output Enable; active low
Write Enable; active low
Chip Enable; active low
Core power supply
Clock Input Signal
Description
Address Inputs
No Connect
Ground
C1
D1
-DQ
-DQ
C9
D9
; active low (x36 Version Only)
; active low (x36 Version Only)
A1
B1
© 2001, Giga Semiconductor, Inc.
-DQ
-DQ
A9
B9
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; active low
; active low