GS8320Z18T ETC, GS8320Z18T Datasheet - Page 8

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GS8320Z18T

Manufacturer Part Number
GS8320Z18T
Description
(GS8320Z18T/36T) 36Mb Pipelined and Flow Through Synchronous NBT SRAM
Manufacturer
ETC
Datasheet
Rev: 1.01 10/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Pipeline and Flow Through Read Write Control State Diagram
Key
Current State and Next State Definition for
Current State (n)
Clock (CK)
Command
ƒ
Transition
Input Command Code
B
R
Current State
Burst Read
New Read
Next State (n+1)
R
n
D
B
ƒ
D
W
R
Pipeline and Flow Through Read/Write Control State Diagram
n+1
Next State
W
8/25
D
Deselect
ƒ
B
R
Notes:
1. The Hold command (CKE Low) is not
2. W, R, B and D represent input command
n+2
shown because it prevents any state change.
codes ,as indicated in the Synchronous Truth Table.
R
GS8320Z18/36T-250/225/200/166/150/133
D
Burst Write
New Write
ƒ
W
D
B
n+3
W
ƒ
B
© 2001, Giga Semiconductor, Inc.
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