GS8320Z18T ETC, GS8320Z18T Datasheet - Page 11

• Manufacturer Part Number: GS8320Z18T
• Description: (GS8320Z18T/36T) 36Mb Pipelined and Flow Through Synchronous NBT SRAM
• Manufacturer: ETC

Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Note:
There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Rev: 1.01 10/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
3rd address
4th address
1st address
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
11
00
Pin Name State
10
11
00
01
LBO
FT
ZZ
11
00
01
10
H or NC
L or NC
H
H
L
L
11/25
Standby, I
I
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst
nterleaved Burst Sequence
Flow Through
Linear Burst
2nd address
Function
3rd address
1st address
4th address
Pipeline
Active
DD
GS8320Z18/36T-250/225/200/166/150/133
= I
SB
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
00
11
10
© 2001, Giga Semiconductor, Inc.
10
11
00
01
Product Preview
11
10
01
00
BPR 1999.05.18