GS82032 ETC, GS82032 Datasheet - Page 5

• Manufacturer Part Number: GS82032
• Description: 64K x 32 2M Synchronous Burst SRAM
• Manufacturer: ETC

Mode Pin Functions
Note:
There are pull-up devices on LBO and FT pins and a pull-down device on the ZZ pin, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock
Byte Write Truth Table
Notes:
1.
2.
3.
Rev: 1.09 7/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1st address
2nd address
3rd address
4th address
Write all bytes
Write all bytes
All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
Byte Write Enable inputs B
All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Write byte
Write byte
Write byte
Write byte
Function
Read
Read
Output Register Control
Power Down Control
Burst Order Control
Mode Name
C
D
A
B
A[1:0]
00
01
10
11
GW
H
H
H
H
H
H
H
L
A[1:0]
A
, B
01
10
00
11
B
, B
C
and/or B
A[1:0]
BW
10
11
00
01
H
L
L
L
L
L
L
X
Pin Name
D
A[1:0]
may be used in any combination with BW to write single or multiple bytes.
.
LBO
00
01
10
ZZ
11
FT
B
X
H
H
H
H
X
L
L
A
5/23
H or NC
H or NC
L or NC
State
H
L
L
B
I
Note: The burst counter wraps to initial state on the 5th clock.
1st address
2nd address
3rd address
4th address
X
H
H
H
H
X
L
L
nterleaved Burst Sequence
B
B
X
H
H
H
H
X
L
L
Standby, I
Interleaved Burst
C
Flow Through
Linear Burst
Function
Pipeline
A[1:0]
Active
00
01
10
11
GS82032AT/Q-180/166/133/100
DD
= I
B
X
H
H
H
H
X
L
L
D
A[1:0]
SB
01
00
11
10
© 2000, Giga Semiconductor, Inc.
A[1:0]
Notes
2, 3, 4
2, 3, 4
2, 3, 4
10
00
01
11
2, 3
2, 3
1
1
A[1:0]
11
10
01
00