GS82032 ETC, GS82032 Datasheet - Page 7

• Manufacturer Part Number: GS82032
• Description: 64K x 32 2M Synchronous Burst SRAM
• Manufacturer: ETC

Notes:
1.
2.
3.
Rev: 1.09 7/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Simplified State Diagram
The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
The upper portion of the diagram assumes active use of only the Enable (E
inputs, and that ADSP is tied high and ADSC is tied low.
The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
X
CW
X
First Write
Burst Write
W
W
CW
7/23
W
CR
R
CR
R
Deselect
X
1,
E
2,
E
3
R
) and Write (B
CR
First Read
Burst Read
R
GS82032AT/Q-180/166/133/100
R
A
, B
B
CR
, B
X
C
X
, B
© 2000, Giga Semiconductor, Inc.
D
, BW, and GW) control