GS82032 ETC, GS82032 Datasheet - Page 8

• Manufacturer Part Number: GS82032
• Description: 64K x 32 2M Synchronous Burst SRAM
• Manufacturer: ETC

Notes:
1.
2.
3.
Rev: 1.09 7/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Simplified State Diagram with G
The diagram shows supported (tested) synchronous state transitions, plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (Read Cycles with G high) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
Transitions shown in gray assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data
Input Set Up Time.
X
X
CW
First Write
Burst Write
W
W
CW
8/23
W
CR
R
CR
R
Deselect
X
CW
W
CW
W
R
CR
First Read
Burst Read
R
GS82032AT/Q-180/166/133/100
R
CR
X
X
© 2000, Giga Semiconductor, Inc.