K4R881869D Samsung semiconductor, K4R881869D Datasheet - Page 14

• Manufacturer Part Number: K4R881869D
• Description: 256/288Mbit RDRAM(D-die)
• Manufacturer: Samsung semiconductor

K4R571669D/K4R881869D
Timing Conditions
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYCLE
CR
CH
TR
DCW
DR
S
DR1,
DR2,
CYCLE1
CH1
S1
H1
S2
H2
S3
H3
S4
H4
NPQ
READTOCC
CCSAMTOREAD
CE
, t
, t
, t
, t
H
, t
Symbol
CF
CL
DF
t
t
DF1
DF2
CL1
CTM and CFM cycle times (-1066)
CTM and CFM cycle times (-800)
CTM and CFM input rise and fall times. Use the minimum value of
these parameters during testing.
CTM and CFM high and low times
CTM-CFM differential (MSE/MS=0/0)
CTM-CFM differential (MSE/MS=1/1)
CTM-CFM differential only for 1.875ns (MSE/MS=1/0)
Domain crossing window
DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use the
minimum value of these parameters during testing.
DQA/DQB/ROW/COL-to-CFM set/hold @ t
DQA/DQB/ROW/COL-to-CFM set/hold @ t
SIO0, SIO1 input rise and fall times
CMD, SCK input rise and fall times
SCK cycle time - Serial control register transactions
SCK cycle time - Power transitions @ t
SCK cycle time - Power transitions @ t
SCK high and low times @ t
SCK high and low times @ t
CMD setup time to SCK rising or falling edge
CMD setup time to SCK rising or falling edge
CMD hold time to SCK rising or falling edge
SIO0 setup time to SCK falling edge
SIO0 hold time to SCK falling edge
PDEV setup time on DQA5..0 to SCK rising edge.
PDEV hold time on DQA5..0 to SCK rising edge.
ROW2..0, COL4..0 setup time for quiet window
ROW2..0, COL4..0 hold time for quiet window
Quiet on ROW/COL bits during NAP/PDN entry
Offset between read data and CC packets (same device)
Offset between CC packet and read data (same device)
CTM/CFM stable before NAP/PDN exit
Parameter
CYCLE
CYCLE
Table 11: Timing Conditions
=1.875ns
=2.50ns
a
CYCLE
CYCLE
d
CYCLE
CYCLE
d
d
=1.875ns
=2.50ns
@ t
e
@ t
Page 12
CYCLE
CYCLE
=1.875ns
=2.50ns
=1.875ns
=2.50ns
0.200
0.160
1.875
Min
1000
40%
4.25
1.25
2.50
-0.1
-0.1
0.2
0.0
0.9
0.2
7.5
3.5
1.0
5.5
10
40
40
12
-1
1
0
5
4
8
2
-
-
b.c
b
Version 1.4 July 2002
Max
60%
3.33
0.45
2.5
0.5
1.0
1.0
0.1
0.1
5.0
2.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Direct RDRAM
t
t
t
t
t
t
t
t
t
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure(s)
Figure 56
Figure 56
Figure 56
Figure 43
Figure 56
Figure 62
Figure 57
Figure 57
Figure 59
Figure 59
Figure 59
Figure 59
Figure 59
Figure 59
Figure 59
Figure 59
Figure 50
Figure 60
Figure 50
Figure 50
Figure 49
Figure 54
Figure 54
Figure 50
™