K4R881869D Samsung semiconductor, K4R881869D Datasheet - Page 5

• Manufacturer Part Number: K4R881869D
• Description: 256/288Mbit RDRAM(D-die)
• Manufacturer: Samsung semiconductor

K4R571669D/K4R881869D
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Signal
SIO1,SIO0
CMD
SCK
V
V
V
GND
GNDa
DQA8..DQA0
CFM
CFMN
V
CTMN
CTM
RQ7..RQ5 or
ROW2..ROW0
RQ4..RQ0 or
COL4..COL0
DQB8..
DQB0
Total pin count per package
DD
DDa
CMOS
REF
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
RSL
Type
CMOS
CMOS
CMOS
RSL
RSL
RSL
RSL
RSL
RSL
RSL
b
b
b
b
b
b
b
b
a
a
a
# Pins
center
24
28
92
2
1
1
1
2
2
9
1
1
1
1
1
3
5
9
Description
Serial input/output. Pins for reading from and writing to the control regis-
ters using a serial access protocol. Also used for power management.
Command input. Pins used in conjunction with SIO0 and SIO1 for reading
from and writing to the control registers. Also used for power manage-
ment.
Serial clock input. Clock source used for reading from and writing to the
control registers
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
Data byte A. Nine pins which carry a byte of read or write data between
the Channel and the RDRAM device. DQA8 is not used (no connection)
by RDRAM device with a x16 organization.
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Negative polarity
Logic threshold reference voltage for RSL signals
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
Row access control. Three pins containing control and address informa-
tion for row accesses.
Column access control. Five pins containing control and address informa-
tion for column accesses.
Data byte B. Nine pins which carry a byte of read or write data between
the Channel and the RDRAM device. DQB8 is not used (no connection)
by RDRAM device with a x16 organization.
Table 2: Pin Description
Page 3
Version 1.4 July 2002
Direct RDRAM
™