K4H510438A-TCA0 SAMSUNG [Samsung semiconductor], K4H510438A-TCA0 Datasheet

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... DDR SDRAM DDR SDRAM Specification Version 1.0 REV. 1.0 November. 2. 2000 - 1 - ...

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... Added QFC Function. - Added DC current value - Reduce I/O capacitance values Version 0.4(Feb,1999) -Added DDR SDRAM history for reference(refer to the following page) -Added low power version DC spec Version 0.5(Apr,1999) -Revised following first showing for JEDEC standard -Added DC target current based on new DC test condition Version 0 ...

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... DDR SDRAM Revision History(continued) Version 0.7 (March, 2000) - Changed 128Mb spec from target to Preliminary version. - Changed partnames as follows. from KM44L32031BT-G(L)Z/Y/0 KM48L16031BT-G(L)Z/Y/0 KM416L8031BT-G(L)Z/Y/0 - Changed input cap. spec. from CK/CK 2.5pF ~ 3.5pF DQ/DQS/DM 4.0pF ~ 5.5pF CMD/Addr 2.5pF ~ 3.5pF - Changed operating condition. from Vil/Vih(ac) Vref +/- 0.35V ...

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... Extended Mode Register Set(EMRS) 3.2.3 Precharge 3.2.4 No Operation(NOP) & Device Deselect 3.2.5 Row Active 3.2.6 Read Bank 3.2.7 Write Bank 3.3 Essential Functionality for DDR SDRAM 3.3.1 Burst Read Operation 3.3.2 Burst Write Operation 3.3.3 Read Interrupted by a Read 3.3.4 Read Interrupted by a Write & Burst Stop 3.3.5 Read Interrupted by a Precharge 3 ...

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... DDR SDRAM 3.3.7 Write Interrupted by a Read & DM 3.3.8 Write Interrupted by a Precharge & DM 3.3.9 Burst Stop 3.3.10 DM masking 3.3.11 Read With Auto Precharge 3.3.12 Write With Auto Precharge 3.3.13 Auto Refresh & Self Refresh 3.3.14 Power Down 4. Command Truth Table 5. Functional Truth Table 6. Absolute Maximum Rating 7. DC Operating Conditions & Specifications 7 ...

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... DDR SDRAM List of tables Table 1 : Operating frequency and DLL jitter Table 2. : Column address configurtion Table 3 : Input/Output function description Table 4 : Burst address ordering for burst length Table 5 : Bank selection for precharge by bank address bits Table 6 : Operating description when new command asserted while ...

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... DDR SDRAM List of figures Figure 1 : 128Mb Package Pinout Figure 2 : Package dimension Figure 3 :State digram Figure 4 : Power up and initialization sequence Figure 5 : Mode register set Figure 6 : Mode register set sequence Figure 7 : Extend mode register set Figure 8 : Bank activation command cycle timing Figure 9 : Burst read operation timing ...

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... Memory DRAM Small Classification Density and Refresh Organization Bank 1. SAMSUNG Memory : K 2. DRAM : 4 3. Small Classification H : DDR SDRAM 4. Density & Refresh 64 : 64M 4K/64ms 28 : 128M 4K/64ms 56 : 256M 8K/64ms 51 : 512M 8K/64ms 16K/32ms 5. Organization x16 32 : x32 6 ...

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... DDR SDRAM 1. Key Features 1.1 Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs - ...

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... DDR SDRAM 1. Package Pinout & Dimension 2.1 Package Pinout DDQ SSQ DDQ SSQ DDQ LDQS QFC/NC QFC/NC LDM WE CAS CAS RAS RAS AP/A AP ...

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... DDR SDRAM 2.2 Input/Output Function Description SYMBOL TYPE CK, CK Input CKE Input CS Input RAS, CAS, WE Input LDM,(U)DM Input BA0, BA1 Input Input DQ I/O LDQS,(U)DQS I/O QFC Output Supply Supply SS V Supply DD V Supply SS V Input REF Table 3. Input/Output Function Description DESCRIPTION Clock : CK and CK are differential clock inputs ...

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... DDR SDRAM 2.3 66 Pin TSOP(II)/MS-024FC Package Physical Dimension #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’Y OUT QUALITY #34 #33 22.22±0.10 (10×) 0.65TYP 0.30±0.08 0.65±0.08 (10×) Figure 2. Package dimension - 12 - Units : Millimeters (10×) +0.075 0.125 -0.035 0.10 MAX [ ] 0.075 MAX 0×~8× REV. 1.0 November. 2. 2000 (10× ...

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... DDR SDRAM 3. Functional Description 3.1 Simplified State Diagram MODE REGISTER SET POWER POWER APPLIED REFS MRS IDLE CKEH POWER ACT DOWN CKEL CKEH ROW ACTIVE WRITE WRITEA READA READ WRITEA WRITE WRITEA READA PRE WRITEA PRE PRE PRE PRE ON CHARGE Figure 3. State diagram ...

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... DDR SDRAM 3.2 Basic Functionality 3.2.1 Power-Up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state(all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & Vref. ...

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... EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS, RAS, CAS, WE and BA0(The DDR SDRAM should be in all bank pre- charge with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A11 in the same cycle as CS, RAS, CAS, WE and BA0 going low are written in the mode register ...

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... DDR SDRAM Burst Length Address(A2, A1, A0 Table 4. Burst address ordering for burst length DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returing to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enabled automatically) ...

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... DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register ...

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... The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs. The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS, CAS and WE. For both Deselect and NOP the device should finish the current operation when this com- mand is issued ...

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... The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The DDR SDRAM has four independent banks, so two Bank Select addresses(BA0, BA1) are required. The Bank Activation command must be applied before any Read or Write operation is exe- cuted ...

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... The essential functionality that is required for the DDR SDRAM device is described in this chapter 3.3.1 Burst Read Operation Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock(CK) after tRCD from the bank activation ...

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... DDR SDRAM 3.3.2 Burst Write Operation The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock(CK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS(Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock(CK) that the write command is issued ...

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... DDR SDRAM 3.3.3 Read Interrupted by a Read A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied ...

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... DQ s Figure 13. Read interrupted by a precharge timing When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank. ...

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... DDR SDRAM 3.3.6 Write Interrupted by a Write A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restric- tion that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied ...

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... For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow the buses to turn around before the DDR SDRAM drives them during a read operation input Write data is masked by the Read command, the DQS input is ignored by the DDR SDRAM. 5. Refer to "3.3.2 Burst write operation" 1 ...

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... Precharge timing for Write operations in DRAMs requires enough time to allow “write recovery” which is the time required by a DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used to indicate the required amount of time between the last valid write operation and a Precharge command to the same bank ...

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... DQS CAS Latency=2 The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required: 1. The BST command may only be issued on the rising edge of the input clock, CK. 2. BST is only a valid command during Read bursts. 3. BST during a Write burst is undefined and shall not be used. ...

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... The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s). 3.3.10 DM masking The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data ...

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... DDR SDRAM 3.3.11 Read With Auto Precharge If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new command can not be asserted until the precharge time(tRP) has been satisfied ...

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... DDR SDRAM 3.3.12 Write with Auto Precharge If A10 is high when write command is issued , the write with auto-precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal pre- charge begins after keeping tWR(min). ...

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... DDR SDRAM 3.3.13 Auto Refresh & Self Refresh Auto Refresh An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the ris- ing edge of the clock(CK). All banks must be precharged and idle for tRP(min) before the auto refresh com- mand is applied ...

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... DDR SDRAM 3.3.14 Power down The power down mode is entered when CKE is low and exited when CKE is high. Once the power down mode is initiated, all of the receiver circuits except clock, CKE and DLL circuit tree are gated off to reduce power consumption. All banks should be in idle state prior to entering the precharge power down mode and CKE should be set high at least 1tck+tIS prior to row active command ...

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... Burst stop command is valid at every burst length sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. CKEn-1 ...

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... DDR SDRAM 5. Functional Truth Table Current State CS RAS CAS PRECHARGE L H STANDBY ACTIVE L H STANDBY READ Address BA, CA ...

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... DDR SDRAM Current State CS RAS CAS WRITE READ with L H AUTO PRECHARGE L H (READA WRITE with L H AUTO RECHARGE L H (WRITEA Address ...

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... DDR SDRAM Current State CS RAS CAS PRECHARG ING L H (DURING tRP ROW L H ACTIVATING L H (FROM ROW L L ACTIVE tRCD WRITE L H RECOVERING L H (DURING tWR tCDLR ...

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... DDR SDRAM Current State CS RAS CAS RE FRESHING MODE L H REGISTER L H SETTING Address BA Op-Code, Mode-Add BA, CA ...

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... DDR SDRAM CKE CKE Current State n-1 n SELF REFRESHING POWER L H DOWN L L ALL BANKS IDLE ANY STATE H H other than listed above ABBREVIATIONS : H=High Level, L=Low level, X=Don t Care Note : 1 ...

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... DDR SDRAM 6. Absolute Maximum Rating Parameter Voltage on any pin relative to V Voltage on V supply relative Voltage on V supply relative to V DDQ Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. ...

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... DDR SDRAM 7.2 DDR SDRAM SPEC Items and Test Conditions Conditions Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating current - One bank operation ...

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... DDR SDRAM 7.3 DDR SDRAM I DD 32Mx4 K4H280438B-TCA2 (DDR266A) Symbol typical IDD0 85 IDD1 125 IDD2P 21 IDD2F 40 IDD2Q 30 IDD3P 25 IDD3N 35 IDD4R 140 IDD4W 125 IDD5 185 IDD6 Normal 2 Low power 1 IDD7 250 16Mx8 K4H280838BT-CA2 (DDR266A) Symbol typical IDD0 90 IDD1 140 IDD2P 21 IDD2F ...

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... IDD7 300 Table 12. 128Mb DDR SDRAM IDD SPEC Table < Detailed test conditions for DDR SDRAM IDD1 & IDD7 > IDD1 : Operating current: One bank operation 1. Typical Case : Vdd = 2.5V, T=25’ Worst Case : Vdd = 2.7V, T= 10’ Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle ...

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... DDR SDRAM DD7 I : Operating current: Four bank operation 1. Typical Case : Vdd = 2.5V, T=25’ Worst Case : Vdd = 2.7V, T= 10’ Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 4. Timing patterns ...

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... DDR SDRAM 8.2 AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time CL=2 ...

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... DDR SDRAM Parameter Exit self refresh to bank active command tXSA Exit self refresh to read command Refresh interval time 64Mb, 128Mb 256Mb Output DQS valid window Clock half period DQS write postamble time QFC setup to first DQS edge on reads QFC hold after last DQS edge on reads ...

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... DDR SDRAM 9. AC Operating Test Conditions (V =2.5V, V =2.5V DDQ A Parameter Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Table 15 ...

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... The nominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b. ...

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... DDR SDRAM Pulldown Current (mA) Typical Typical Voltage (V) Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 0.6 34.6 39.1 0.7 39.4 44.2 0.8 43.7 49.8 0.9 47.5 55.2 1.0 51.3 60.3 1.1 54.1 65.2 1.2 56.2 69.9 1.3 57.9 74.2 1.4 59.3 78.4 1.5 60.1 82.3 1.6 60.5 85.9 1.7 61.0 89.1 1.8 61.5 92.2 1.9 62.0 95.3 2.0 62.5 97.2 2.1 62.9 99.1 2.2 63.3 100.9 2.3 63.8 101.9 2.4 64.1 102.8 2.5 64.6 103.8 2.6 64.8 104.6 2.7 65.0 105.4 Temperature (Tambient) Typical 25 C Minimum 70 C Maximum 0 C Vdd/Vddq Typical 2.5V Minimum 2.3V Maximum 2.7V The above characteristics are specified under best, worst and normal process variation/conditions Minimum Maximum 4 ...

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... Thenominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b. ...

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... DDR SDRAM Pulldown Current (mA) Typical Typical Voltage (V) Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.6 22.1 0.7 22.3 25.0 0.8 24.7 28.2 0.9 26.9 31.3 1.0 29.0 34.1 1.1 30.6 36.9 1.2 31.8 39.5 1.3 32.8 42.0 1.4 33.5 44.4 1.5 34.0 46.6 1.6 34.3 48.6 1.7 34.5 50.5 1.8 34.8 52.2 1.9 35.1 53.9 2.0 35.4 55.0 2.1 35.6 56.1 2.2 35.8 57.1 2.3 36.1 57.7 2.4 36.3 58.2 2.5 36.5 58.7 2.6 36.7 59.2 2.7 36.8 59.6 Temperature (Tambient) Typical 25 C Minimum 70 C Maximum 0 C Vdd/Vddq Typical 2.5V Minimum 2.3V Maximum 2.7V The above characteristics are specified under best, worst and normal process variation/conditions Minimum Maximum 2.6 5.0 5.2 9.9 7.8 14.6 10.4 19.2 13.0 23.6 15.7 28.0 18.2 32.2 20.8 35.8 22.4 39.5 24.1 43.2 25.4 46.7 26.2 50.0 26.6 53.1 26.8 56.1 27.0 58.7 27.2 61.4 27.4 63.5 27.7 65.6 27.8 67.7 28.0 69.8 28.1 71.6 28.2 73.3 28.3 74.9 28.3 76.4 28.4 77.7 28.5 78.8 28.6 79.7 Table 18. Pull down and pull up current values ...

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... QFC function QFC definition when drive low on reads coincident with the start of DQS, this DRAM output signal says that one cycle later there will be the first valid DQS output and returned to HI-Z after this finishing a burst operation also driven low shortly after a write command is received and returned to HI-Z shortly after the last data strobe transition is received ...

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... DDR SDRAM QFC timing on Write operation QFC on writes is enabled as soon as possible after the clock edge of write command and disabled as soon as possible after the last DQS-in low going edge Command Write DQS@tDQSSmax DQ’ S @tDQSSmax Hi-Z t QFC Figure 27. : QFC timing on write operation with tDQSSmax ...

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... DDR SDRAM QFC timing example for interrupted Writes operation Command Write DQS DQ’ S Hi-Z QFC t QCSW Figure 29. : QFC timing example for Interrupted writes operation Precharge Dout 2 Dout 3 Dout 0 Dout QCHWI max REV. 1.0 November. 2. 2000 ...