K4H510438A-TCA0 SAMSUNG [Samsung semiconductor], K4H510438A-TCA0 Datasheet - Page 24

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K4H510438A-TCA0

Manufacturer Part Number
K4H510438A-TCA0
Description
128Mb DDR SDRAM
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
128Mb DDR SDRAM
3.3.6 Write Interrupted by a Write
tion that the interval that separates the commands must be at least one clock cycle. When the previous burst
is interrupted, the remaining addresses are overridden by the new address and data will be written into the
device until the programmed burst length is satisfied.
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restric-
< Burst Length=4 >
Command
DQS
DQ s
CK
CK
NOP
0
Figure 14. Write interrupted by a write timing
WRITE A
1
1t
CK
WRITE b
Din A
0
2
Din A
- 24 -
1
Din B
NOP
0
3
Din B
1
Din B
NOP
4
2
REV. 1.0 November. 2. 2000
Din B
3
NOP
5
NOP
6
NOP
7
NOP
8

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