K4H510438A-TCA0 SAMSUNG [Samsung semiconductor], K4H510438A-TCA0 Datasheet - Page 16

• Manufacturer Part Number: K4H510438A-TCA0
• Description: 128Mb DDR SDRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

128Mb DDR SDRAM
DLL Enable/Disable
upon returing to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon
exiting Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles
must occur before a READ command can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. Some vendors might also support
a weak driver strength option, intended for lighter load and/or point-to-point environments. I-V curves for the
normal drive strength and weak drive strength will be included in a future revision of this document.
*1 : MRS can be issued only at all bank precharge state.
*2 : Minimum
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and
Mode Register Set
Command
t
RP
CK
CK
is required to issue MRS command.
Length
Burst
2
4
8
0
t
CK
Precharge
Address(A2, A1, A0)
All Banks
Table 4. Burst address ordering for burst length
1
Starting
000
001
010
011
100
101
110
111
xx0
xx1
x00
x01
x10
x11
Burst Address Ordering for Burst Length
Figure 6. Mode Register Set sequence
t
RP
*2
2
Register Set
*1
Mode
- 16 -
3
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
Sequential Mode
2 Clock min.
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1
1, 0
4
Command
Any
REV. 1.0 November. 2. 2000
5
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Interleave Mode
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
6
0, 1
1, 0
7
8