SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 100

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
6.5.1
100
POLL DEVICE AGAIN
Figure 19. Polling Flow Chart
SERVICE DMA REQUEST
CHANGE DIRECTION
RETURN ID TO HOST
RESET PRINTER
Software-Activated Service Examples (Poll)
The scanning loop for Poll-mode operation is shown in
context switch is performed in the same manner, but termination of the service is done in two ways.
The first method is similar to the serial channel method and the second method can work well in
certain systems, but requires extra steps.
The first method follows the same basic procedure as the serial channels, but the termination
sequence requires only that the upper bit (PPIreq) of the PIR is cleared by the CPU. Since Fair
Share is not implemented on the parallel channel, there is no ‘unfair’ bit in the PIR; the ‘busy’
status is maintained by the MPU differently and is not maintained in the PIR.
DMAREQ
DirCh
SET
SERVICE NEGOTIATION
HARDWARE RESET
INITIALIZE DEVICE
SOFTWARE RESET
CHANGE
PCISR
SVRR
TEST
TEST
TEST
TEST
NSR
PIR
PPort SET
SRP SET
NegCh SET
SigCh
Pipeline SET
POLL DEVICE AGAIN
INTERRUPT
SERVICE
CHANGE
SIGNAL
NOTE: It may not be necessary to poll the PFSR if
TEST
SSR
Section
DMA requests are enabled. With DMA
requests enabled, the DMAREQ bit
(SVRR[7]) can be polled to determine
when a FIFO threshold is exceeded. If
DMA requests are disabled, the PFSR
must be polled to determine when to move
data to and from the FIFO. If DMA requests
are enabled, data must be read through the
DMABUF register; this requires a 16-bit
data bus.
INTERRUPT
SERVICE
ERROR
TEST
PFSR
PFSR
TEST
6.3. Software activation of the
= 00H
DataErr
APPROPRIATE
REGISTER
HOLDING
SERVICE
EMPTY
FF FULL
HRSR
TEST
HR DATA
HR TAG
(transmiting)
OR
OR
(receiving)
Datasheet
SERVICE
FIFO